[llvm] [X86] LowerSelect - generalize "select icmp(x,0), lhs, rhs" folding patterns. (PR #107272)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 10:35:10 PDT 2024
https://github.com/RKSimon updated https://github.com/llvm/llvm-project/pull/107272
>From bd45d9776e142b208c3c7805b36f4f8fd4287562 Mon Sep 17 00:00:00 2001
From: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: Wed, 4 Sep 2024 18:22:16 +0100
Subject: [PATCH] [X86] LowerSelect - generalize "select icmp(x,0), lhs, rhs"
folding patterns.
Special case lowering when we're selecting from a compare-with-zero condition assumes that the compare came from a X86ISD::SETCC node.
But we have many cases where the condition is a "(and x, 1)" pattern (e.g. from a bool argument or some other simplified bitlogic), and we have a large number of existing generic/x86 patterns that make use of this (and trying to convert to a SETCC node can cause infinite loops).
This patch proposes we add a LowerSELECTWithCmpZero helper, which allows us to fold the compare-with-zero from different condition nodes with minimal duplication.
So far I've only handled the simple no-cmov case for or/xor nodes, but the intention is to convert more folds in future PRs.
---
llvm/lib/Target/X86/X86ISelLowering.cpp | 96 ++++++++-----
.../pull-conditional-binop-through-shift.ll | 132 ++++++++----------
llvm/test/CodeGen/X86/select.ll | 36 +++--
3 files changed, 136 insertions(+), 128 deletions(-)
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 451881e1d61415..3fc8a1a074fcba 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -24074,6 +24074,55 @@ static bool isTruncWithZeroHighBitsInput(SDValue V, SelectionDAG &DAG) {
return DAG.MaskedValueIsZero(VOp0, APInt::getHighBitsSet(InBits,InBits-Bits));
}
+// Lower various (select (icmp CmpVal, 0), LHS, RHS) custom patterns.
+static SDValue LowerSELECTWithCmpZero(SDValue CmpVal, SDValue LHS, SDValue RHS,
+ unsigned X86CC, const SDLoc &DL,
+ SelectionDAG &DAG,
+ const X86Subtarget &Subtarget) {
+ EVT CmpVT = CmpVal.getValueType();
+ EVT VT = LHS.getValueType();
+ if (!CmpVT.isScalarInteger() || !VT.isScalarInteger())
+ return SDValue();
+
+ if (!Subtarget.canUseCMOV() && X86CC == X86::COND_E &&
+ CmpVal.getOpcode() == ISD::AND && isOneConstant(CmpVal.getOperand(1))) {
+ SDValue Src1, Src2;
+ // true if RHS is XOR or OR operator and one of its operands
+ // is equal to LHS
+ // ( a , a op b) || ( b , a op b)
+ auto isOrXorPattern = [&]() {
+ if ((RHS.getOpcode() == ISD::XOR || RHS.getOpcode() == ISD::OR) &&
+ (RHS.getOperand(0) == LHS || RHS.getOperand(1) == LHS)) {
+ Src1 = RHS.getOperand(RHS.getOperand(0) == LHS ? 1 : 0);
+ Src2 = LHS;
+ return true;
+ }
+ return false;
+ };
+
+ if (isOrXorPattern()) {
+ SDValue Neg;
+ unsigned int CmpSz = CmpVT.getSizeInBits();
+ // we need mask of all zeros or ones with same size of the other
+ // operands.
+ if (CmpSz > VT.getSizeInBits())
+ Neg = DAG.getNode(ISD::TRUNCATE, DL, VT, CmpVal);
+ else if (CmpSz < VT.getSizeInBits())
+ Neg = DAG.getNode(
+ ISD::AND, DL, VT,
+ DAG.getNode(ISD::ANY_EXTEND, DL, VT, CmpVal.getOperand(0)),
+ DAG.getConstant(1, DL, VT));
+ else
+ Neg = CmpVal;
+ SDValue Mask = DAG.getNegative(Neg, DL, VT); // -(and (x, 0x1))
+ SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
+ return DAG.getNode(RHS.getOpcode(), DL, VT, And, Src2); // And Op y
+ }
+ }
+
+ return SDValue();
+}
+
SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
bool AddTest = true;
SDValue Cond = Op.getOperand(0);
@@ -24195,7 +24244,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
(CondCode == X86::COND_E && MatchFFSMinus1(Op2, Op1)))) {
// Keep Cmp.
} else if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
- (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
+ (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
SDValue Y = isAllOnesConstant(Op2) ? Op1 : Op2;
SDVTList CmpVTs = DAG.getVTList(CmpOp0.getValueType(), MVT::i32);
@@ -24218,41 +24267,9 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
DAG.getTargetConstant(X86::COND_B, DL, MVT::i8),
Sub.getValue(1));
return DAG.getNode(ISD::OR, DL, VT, SBB, Y);
- } else if (!Subtarget.canUseCMOV() && CondCode == X86::COND_E &&
- CmpOp0.getOpcode() == ISD::AND &&
- isOneConstant(CmpOp0.getOperand(1))) {
- SDValue Src1, Src2;
- // true if Op2 is XOR or OR operator and one of its operands
- // is equal to Op1
- // ( a , a op b) || ( b , a op b)
- auto isOrXorPattern = [&]() {
- if ((Op2.getOpcode() == ISD::XOR || Op2.getOpcode() == ISD::OR) &&
- (Op2.getOperand(0) == Op1 || Op2.getOperand(1) == Op1)) {
- Src1 =
- Op2.getOperand(0) == Op1 ? Op2.getOperand(1) : Op2.getOperand(0);
- Src2 = Op1;
- return true;
- }
- return false;
- };
-
- if (isOrXorPattern()) {
- SDValue Neg;
- unsigned int CmpSz = CmpOp0.getSimpleValueType().getSizeInBits();
- // we need mask of all zeros or ones with same size of the other
- // operands.
- if (CmpSz > VT.getSizeInBits())
- Neg = DAG.getNode(ISD::TRUNCATE, DL, VT, CmpOp0);
- else if (CmpSz < VT.getSizeInBits())
- Neg = DAG.getNode(ISD::AND, DL, VT,
- DAG.getNode(ISD::ANY_EXTEND, DL, VT, CmpOp0.getOperand(0)),
- DAG.getConstant(1, DL, VT));
- else
- Neg = CmpOp0;
- SDValue Mask = DAG.getNegative(Neg, DL, VT); // -(and (x, 0x1))
- SDValue And = DAG.getNode(ISD::AND, DL, VT, Mask, Src1); // Mask & z
- return DAG.getNode(Op2.getOpcode(), DL, VT, And, Src2); // And Op y
- }
+ } else if (SDValue R = LowerSELECTWithCmpZero(CmpOp0, Op1, Op2, CondCode,
+ DL, DAG, Subtarget)) {
+ return R;
} else if ((VT == MVT::i32 || VT == MVT::i64) && isNullConstant(Op2) &&
Cmp.getNode()->hasOneUse() && (CmpOp0 == Op1) &&
((CondCode == X86::COND_S) || // smin(x, 0)
@@ -24278,6 +24295,13 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
isOneConstant(Cond.getOperand(1)))
Cond = Cond.getOperand(0);
+ // Attempt to fold "raw cond" cases by treating them as
+ // (select (and X, 1), Op1, Op2 --> (select (icmpeq (and X, 1), 0), Op2, Op1)
+ if (Cond.getOpcode() == ISD::AND && isOneConstant(Cond.getOperand(1)))
+ if (SDValue R = LowerSELECTWithCmpZero(Cond, Op2, Op1, X86::COND_E, DL, DAG,
+ Subtarget))
+ return R;
+
// If condition flag is set by a X86ISD::CMP, then use it as the condition
// setting operand in place of the X86ISD::SETCC.
unsigned CondOpcode = Cond.getOpcode();
diff --git a/llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll b/llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll
index 4f39b8f945413c..def4c08a3592ec 100644
--- a/llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll
+++ b/llvm/test/CodeGen/X86/pull-conditional-binop-through-shift.ll
@@ -77,12 +77,11 @@ define i32 @or_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_signbit_select_shl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB2_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $16711680, %eax # imm = 0xFF0000
-; X86-NEXT: .LBB2_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $16711680, %eax # imm = 0xFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -106,12 +105,11 @@ define i32 @or_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_nosignbit_select_shl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB3_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $16711680, %eax # imm = 0xFF0000
-; X86-NEXT: .LBB3_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $16711680, %eax # imm = 0xFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -136,12 +134,11 @@ define i32 @xor_signbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_signbit_select_shl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB4_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $16711680, %eax # imm = 0xFF0000
-; X86-NEXT: .LBB4_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $16711680, %eax # imm = 0xFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -165,12 +162,11 @@ define i32 @xor_nosignbit_select_shl(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_nosignbit_select_shl:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB5_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $16711680, %eax # imm = 0xFF0000
-; X86-NEXT: .LBB5_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $16711680, %eax # imm = 0xFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shll $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -315,12 +311,11 @@ define i32 @or_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_signbit_select_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB10_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
-; X86-NEXT: .LBB10_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -344,12 +339,11 @@ define i32 @or_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_nosignbit_select_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB11_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
-; X86-NEXT: .LBB11_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -374,12 +368,11 @@ define i32 @xor_signbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_signbit_select_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB12_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
-; X86-NEXT: .LBB12_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -403,12 +396,11 @@ define i32 @xor_nosignbit_select_lshr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_nosignbit_select_lshr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB13_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
-; X86-NEXT: .LBB13_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: shrl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -553,12 +545,11 @@ define i32 @or_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_signbit_select_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB18_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $-65536, %eax # imm = 0xFFFF0000
-; X86-NEXT: .LBB18_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sarl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -582,12 +573,11 @@ define i32 @or_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: or_nosignbit_select_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB19_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: orl $2147418112, %eax # imm = 0x7FFF0000
-; X86-NEXT: .LBB19_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
+; X86-NEXT: orl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sarl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -612,12 +602,11 @@ define i32 @xor_signbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_signbit_select_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB20_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $-65536, %eax # imm = 0xFFFF0000
-; X86-NEXT: .LBB20_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $-65536, %eax # imm = 0xFFFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sarl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
@@ -641,12 +630,11 @@ define i32 @xor_nosignbit_select_ashr(i32 %x, i1 %cond, ptr %dst) {
; X86-LABEL: xor_nosignbit_select_ashr:
; X86: # %bb.0:
; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx
-; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT: testb $1, {{[0-9]+}}(%esp)
-; X86-NEXT: je .LBB21_2
-; X86-NEXT: # %bb.1:
-; X86-NEXT: xorl $2147418112, %eax # imm = 0x7FFF0000
-; X86-NEXT: .LBB21_2:
+; X86-NEXT: movzbl {{[0-9]+}}(%esp), %eax
+; X86-NEXT: andl $1, %eax
+; X86-NEXT: negl %eax
+; X86-NEXT: andl $2147418112, %eax # imm = 0x7FFF0000
+; X86-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X86-NEXT: sarl $8, %eax
; X86-NEXT: movl %eax, (%ecx)
; X86-NEXT: retl
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index ca5558561a65b9..f370ac0a8c7c55 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -1475,11 +1475,10 @@ define i16 @select_xor_1b(i16 %A, i8 %cond) {
;
; MCU-LABEL: select_xor_1b:
; MCU: # %bb.0: # %entry
-; MCU-NEXT: testb $1, %dl
-; MCU-NEXT: je .LBB29_2
-; MCU-NEXT: # %bb.1:
-; MCU-NEXT: xorl $43, %eax
-; MCU-NEXT: .LBB29_2: # %entry
+; MCU-NEXT: andl $1, %edx
+; MCU-NEXT: negl %edx
+; MCU-NEXT: andl $43, %edx
+; MCU-NEXT: xorl %edx, %eax
; MCU-NEXT: # kill: def $ax killed $ax killed $eax
; MCU-NEXT: retl
entry:
@@ -1545,11 +1544,10 @@ define i32 @select_xor_2b(i32 %A, i32 %B, i8 %cond) {
;
; MCU-LABEL: select_xor_2b:
; MCU: # %bb.0: # %entry
-; MCU-NEXT: testb $1, %cl
-; MCU-NEXT: je .LBB31_2
-; MCU-NEXT: # %bb.1:
-; MCU-NEXT: xorl %edx, %eax
-; MCU-NEXT: .LBB31_2: # %entry
+; MCU-NEXT: andl $1, %ecx
+; MCU-NEXT: negl %ecx
+; MCU-NEXT: andl %edx, %ecx
+; MCU-NEXT: xorl %ecx, %eax
; MCU-NEXT: retl
entry:
%and = and i8 %cond, 1
@@ -1614,11 +1612,10 @@ define i32 @select_or_b(i32 %A, i32 %B, i8 %cond) {
;
; MCU-LABEL: select_or_b:
; MCU: # %bb.0: # %entry
-; MCU-NEXT: testb $1, %cl
-; MCU-NEXT: je .LBB33_2
-; MCU-NEXT: # %bb.1:
-; MCU-NEXT: orl %edx, %eax
-; MCU-NEXT: .LBB33_2: # %entry
+; MCU-NEXT: andl $1, %ecx
+; MCU-NEXT: negl %ecx
+; MCU-NEXT: andl %edx, %ecx
+; MCU-NEXT: orl %ecx, %eax
; MCU-NEXT: retl
entry:
%and = and i8 %cond, 1
@@ -1683,11 +1680,10 @@ define i32 @select_or_1b(i32 %A, i32 %B, i32 %cond) {
;
; MCU-LABEL: select_or_1b:
; MCU: # %bb.0: # %entry
-; MCU-NEXT: testb $1, %cl
-; MCU-NEXT: je .LBB35_2
-; MCU-NEXT: # %bb.1:
-; MCU-NEXT: orl %edx, %eax
-; MCU-NEXT: .LBB35_2: # %entry
+; MCU-NEXT: andl $1, %ecx
+; MCU-NEXT: negl %ecx
+; MCU-NEXT: andl %edx, %ecx
+; MCU-NEXT: orl %ecx, %eax
; MCU-NEXT: retl
entry:
%and = and i32 %cond, 1
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