[llvm] [AArch64] Generate rev16 for certain uses of __builtin_bswap16 (PR #105375)

[David Green via llvm-commits]

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@@ -22137,6 +22137,22 @@ static SDValue performExtendCombine(SDNode *N,
       N->getOperand(0)->getOpcode() == ISD::SETCC)
     return performSignExtendSetCCCombine(N, DCI, DAG);
 
+  // If we see (any_extend (bswap ...)) with bswap returning an i16, we know
+  // that the top half of the result register must be unused, due to the
+  // any_extend. This means that we can replace this pattern with (rev16
+  // (any_extend ...)). This saves a machine instruction compared to (lsr (rev
+  // ...)), which is what this pattern would otherwise be lowered to.
+  if (N->getOpcode() == ISD::ANY_EXTEND &&
+      N->getOperand(0).getOpcode() == ISD::BSWAP &&
+      N->getOperand(0).getValueType().isScalarInteger() &&
+      N->getOperand(0).getValueType().getFixedSizeInBits() == 16) {
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davemgreen wrote:

Yeah, Adding i64 sounds like a good idea. We can just add a new tablegen pattern for REV16Xr if I understand it correctly.

Usually with the way types legalize, if you handle i32 and i64 then the other types will follow suit, as they get legalized to i32/i64 anyway. We just need to make sure we don't generate a i128 AArch64ISD::REV16 that cannot be selected.

https://github.com/llvm/llvm-project/pull/105375