[llvm] [AArch64] Generate rev16 for certain uses of __builtin_bswap16 (PR #105375)

[via llvm-commits]

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@@ -22137,6 +22137,22 @@ static SDValue performExtendCombine(SDNode *N,
       N->getOperand(0)->getOpcode() == ISD::SETCC)
     return performSignExtendSetCCCombine(N, DCI, DAG);
 
+  // If we see (any_extend (bswap ...)) with bswap returning an i16, we know
+  // that the top half of the result register must be unused, due to the
+  // any_extend. This means that we can replace this pattern with (rev16
+  // (any_extend ...)). This saves a machine instruction compared to (lsr (rev
+  // ...)), which is what this pattern would otherwise be lowered to.
+  if (N->getOpcode() == ISD::ANY_EXTEND &&
+      N->getOperand(0).getOpcode() == ISD::BSWAP &&
+      N->getOperand(0).getValueType().isScalarInteger() &&
+      N->getOperand(0).getValueType().getFixedSizeInBits() == 16) {
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adprasad-nvidia wrote:

By input type, I assume you mean the input type to the rev16 / output type of the old `any_extend`? As far as I can tell, this is only ever an i32. If an i64 is needed than a `zero_extend` is generated instead. 
In the absence of writing a test, do you think it would be worthwhile to write a comment explaining this? 
Regardless, using `N->getValueType(0)` instead of `EVT(MVT::i32)`, as you suggested, means the logic in the code is independent of whether it is i64 or i32, and so doesn't need a separate pattern in the code. 

https://github.com/llvm/llvm-project/pull/105375