[llvm] [Windows SEH] fix failed assert and crash (PR #107031)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 4 05:26:13 PDT 2024
https://github.com/R-Goc updated https://github.com/llvm/llvm-project/pull/107031
>From 24a7943569db48c1e70b30cce92145f49e5e6f25 Mon Sep 17 00:00:00 2001
From: R-Goc <ryszardgoc at gmail.com>
Date: Tue, 3 Sep 2024 02:37:44 +0200
Subject: [PATCH 1/4] [Windows SEH] fix failed assert and crash
---
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 565 ++++++++++--------
1 file changed, 300 insertions(+), 265 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b37e54d66ddf51..22a4cb04d717ef 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -121,7 +121,8 @@ STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
-STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
+STATISTIC(NumDAGIselRetries,
+ "Number of times dag isel has to try another path");
STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
STATISTIC(NumFastIselFailLowerArguments,
"Number of entry blocks where fast isel failed to lower arguments");
@@ -139,23 +140,22 @@ static cl::opt<bool> EnableFastISelFallbackReport(
cl::desc("Emit a diagnostic when \"fast\" instruction selection "
"falls back to SelectionDAG."));
-static cl::opt<bool>
-UseMBPI("use-mbpi",
- cl::desc("use Machine Branch Probability Info"),
- cl::init(true), cl::Hidden);
+static cl::opt<bool> UseMBPI("use-mbpi",
+ cl::desc("use Machine Branch Probability Info"),
+ cl::init(true), cl::Hidden);
#ifndef NDEBUG
-static cl::opt<std::string>
-FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
- cl::desc("Only display the basic block whose name "
- "matches this for all view-*-dags options"));
-static cl::opt<bool>
-ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before the first "
- "dag combine pass"));
+static cl::opt<std::string> FilterDAGBasicBlockName(
+ "filter-view-dags", cl::Hidden,
+ cl::desc("Only display the basic block whose name "
+ "matches this for all view-*-dags options"));
static cl::opt<bool>
-ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before legalize types"));
+ ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before the first "
+ "dag combine pass"));
+static cl::opt<bool> ViewLegalizeTypesDAGs(
+ "view-legalize-types-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before legalize types"));
static cl::opt<bool>
ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the post "
@@ -164,18 +164,18 @@ static cl::opt<bool>
ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize"));
static cl::opt<bool>
-ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before the second "
- "dag combine pass"));
-static cl::opt<bool>
-ViewISelDAGs("view-isel-dags", cl::Hidden,
- cl::desc("Pop up a window to show isel dags as they are selected"));
-static cl::opt<bool>
-ViewSchedDAGs("view-sched-dags", cl::Hidden,
- cl::desc("Pop up a window to show sched dags as they are processed"));
-static cl::opt<bool>
-ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
- cl::desc("Pop up a window to show SUnit dags after they are processed"));
+ ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before the second "
+ "dag combine pass"));
+static cl::opt<bool> ViewISelDAGs(
+ "view-isel-dags", cl::Hidden,
+ cl::desc("Pop up a window to show isel dags as they are selected"));
+static cl::opt<bool> ViewSchedDAGs(
+ "view-sched-dags", cl::Hidden,
+ cl::desc("Pop up a window to show sched dags as they are processed"));
+static cl::opt<bool> ViewSUnitDAGs(
+ "view-sunit-dags", cl::Hidden,
+ cl::desc("Pop up a window to show SUnit dags after they are processed"));
#else
static const bool ViewDAGCombine1 = false, ViewLegalizeTypesDAGs = false,
ViewDAGCombineLT = false, ViewLegalizeDAGs = false,
@@ -193,7 +193,9 @@ static const bool ViewDAGCombine1 = false, ViewLegalizeTypesDAGs = false,
} \
} while (false)
#else
-#define ISEL_DUMP(X) do { } while (false)
+#define ISEL_DUMP(X) \
+ do { \
+ } while (false)
#endif
//===---------------------------------------------------------------------===//
@@ -211,14 +213,13 @@ MachinePassRegistry<RegisterScheduler::FunctionPassCtor>
//===---------------------------------------------------------------------===//
static cl::opt<RegisterScheduler::FunctionPassCtor, false,
RegisterPassParser<RegisterScheduler>>
-ISHeuristic("pre-RA-sched",
- cl::init(&createDefaultScheduler), cl::Hidden,
- cl::desc("Instruction schedulers available (before register"
- " allocation):"));
+ ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::Hidden,
+ cl::desc("Instruction schedulers available (before register"
+ " allocation):"));
static RegisterScheduler
-defaultListDAGScheduler("default", "Best scheduler for the target",
- createDefaultScheduler);
+ defaultListDAGScheduler("default", "Best scheduler for the target",
+ createDefaultScheduler);
static bool dontUseFastISelFor(const Function &Fn) {
// Don't enable FastISel for functions with swiftasync Arguments.
@@ -232,83 +233,82 @@ static bool dontUseFastISelFor(const Function &Fn) {
namespace llvm {
- //===--------------------------------------------------------------------===//
- /// This class is used by SelectionDAGISel to temporarily override
- /// the optimization level on a per-function basis.
- class OptLevelChanger {
- SelectionDAGISel &IS;
- CodeGenOptLevel SavedOptLevel;
- bool SavedFastISel;
-
- public:
- OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
- : IS(ISel) {
- SavedOptLevel = IS.OptLevel;
- SavedFastISel = IS.TM.Options.EnableFastISel;
- if (NewOptLevel != SavedOptLevel) {
- IS.OptLevel = NewOptLevel;
- IS.TM.setOptLevel(NewOptLevel);
- LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
- << IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel)
- << " ; After: -O" << static_cast<int>(NewOptLevel)
- << "\n");
- if (NewOptLevel == CodeGenOptLevel::None)
- IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
- }
- if (dontUseFastISelFor(IS.MF->getFunction()))
- IS.TM.setFastISel(false);
- LLVM_DEBUG(
- dbgs() << "\tFastISel is "
- << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
- << "\n");
- }
+//===--------------------------------------------------------------------===//
+/// This class is used by SelectionDAGISel to temporarily override
+/// the optimization level on a per-function basis.
+class OptLevelChanger {
+ SelectionDAGISel &IS;
+ CodeGenOptLevel SavedOptLevel;
+ bool SavedFastISel;
- ~OptLevelChanger() {
- if (IS.OptLevel == SavedOptLevel)
- return;
- LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
+public:
+ OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
+ : IS(ISel) {
+ SavedOptLevel = IS.OptLevel;
+ SavedFastISel = IS.TM.Options.EnableFastISel;
+ if (NewOptLevel != SavedOptLevel) {
+ IS.OptLevel = NewOptLevel;
+ IS.TM.setOptLevel(NewOptLevel);
+ LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
- << " ; After: -O" << static_cast<int>(SavedOptLevel) << "\n");
- IS.OptLevel = SavedOptLevel;
- IS.TM.setOptLevel(SavedOptLevel);
- IS.TM.setFastISel(SavedFastISel);
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel)
+ << " ; After: -O" << static_cast<int>(NewOptLevel)
+ << "\n");
+ if (NewOptLevel == CodeGenOptLevel::None)
+ IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
}
- };
+ if (dontUseFastISelFor(IS.MF->getFunction()))
+ IS.TM.setFastISel(false);
+ LLVM_DEBUG(dbgs() << "\tFastISel is "
+ << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
+ << "\n");
+ }
- //===--------------------------------------------------------------------===//
- /// createDefaultScheduler - This creates an instruction scheduler appropriate
- /// for the target.
- ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
- CodeGenOptLevel OptLevel) {
- const TargetLowering *TLI = IS->TLI;
- const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
-
- // Try first to see if the Target has its own way of selecting a scheduler
- if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
- return SchedulerCtor(IS, OptLevel);
- }
+ ~OptLevelChanger() {
+ if (IS.OptLevel == SavedOptLevel)
+ return;
+ LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
+ << IS.MF->getFunction().getName() << "\n");
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
+ << " ; After: -O" << static_cast<int>(SavedOptLevel)
+ << "\n");
+ IS.OptLevel = SavedOptLevel;
+ IS.TM.setOptLevel(SavedOptLevel);
+ IS.TM.setFastISel(SavedFastISel);
+ }
+};
- if (OptLevel == CodeGenOptLevel::None ||
- (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
- TLI->getSchedulingPreference() == Sched::Source)
- return createSourceListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::RegPressure)
- return createBURRListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Hybrid)
- return createHybridListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::VLIW)
- return createVLIWDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Fast)
- return createFastDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Linearize)
- return createDAGLinearizer(IS, OptLevel);
- assert(TLI->getSchedulingPreference() == Sched::ILP &&
- "Unknown sched type!");
- return createILPListDAGScheduler(IS, OptLevel);
+//===--------------------------------------------------------------------===//
+/// createDefaultScheduler - This creates an instruction scheduler appropriate
+/// for the target.
+ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel OptLevel) {
+ const TargetLowering *TLI = IS->TLI;
+ const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
+
+ // Try first to see if the Target has its own way of selecting a scheduler
+ if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
+ return SchedulerCtor(IS, OptLevel);
}
+ if (OptLevel == CodeGenOptLevel::None ||
+ (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
+ TLI->getSchedulingPreference() == Sched::Source)
+ return createSourceListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::RegPressure)
+ return createBURRListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Hybrid)
+ return createHybridListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::VLIW)
+ return createVLIWDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Fast)
+ return createFastDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Linearize)
+ return createDAGLinearizer(IS, OptLevel);
+ assert(TLI->getSchedulingPreference() == Sched::ILP && "Unknown sched type!");
+ return createILPListDAGScheduler(IS, OptLevel);
+}
+
} // end namespace llvm
MachineBasicBlock *
@@ -316,8 +316,8 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const {
#ifndef NDEBUG
dbgs() << "If a target marks an instruction with "
- "'usesCustomInserter', it must implement "
- "TargetLowering::EmitInstrWithCustomInserter!\n";
+ "'usesCustomInserter', it must implement "
+ "TargetLowering::EmitInstrWithCustomInserter!\n";
#endif
llvm_unreachable(nullptr);
}
@@ -396,7 +396,7 @@ SelectionDAGISel::~SelectionDAGISel() {
void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
CodeGenOptLevel OptLevel = Selector->OptLevel;
if (OptLevel != CodeGenOptLevel::None)
- AU.addRequired<AAResultsWrapperPass>();
+ AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<GCModuleInfo>();
AU.addRequired<StackProtector>();
AU.addPreserved<GCModuleInfo>();
@@ -406,14 +406,14 @@ void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
#endif
AU.addRequired<AssumptionCacheTracker>();
if (UseMBPI && OptLevel != CodeGenOptLevel::None)
- AU.addRequired<BranchProbabilityInfoWrapperPass>();
+ AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
// AssignmentTrackingAnalysis only runs if assignment tracking is enabled for
// the module.
AU.addRequired<AssignmentTrackingAnalysis>();
AU.addPreserved<AssignmentTrackingAnalysis>();
if (OptLevel != CodeGenOptLevel::None)
- LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
+ LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -658,7 +658,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// Insert copies in the entry block and the return blocks.
if (FuncInfo->SplitCSR) {
- SmallVector<MachineBasicBlock*, 4> Returns;
+ SmallVector<MachineBasicBlock *, 4> Returns;
// Collect all the return blocks.
for (MachineBasicBlock &MBB : mf) {
if (!MBB.succ_empty())
@@ -857,7 +857,8 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
// Lower the instructions. If a call is emitted as a tail call, cease emitting
// nodes for this block. If an instruction is elided, don't emit it, but do
// handle any debug-info attached to it.
- for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
+ for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall;
+ ++I) {
if (!ElidedArgCopyInstrs.count(&*I))
SDB->visit(*I);
else
@@ -876,7 +877,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode *, 16> Added;
- SmallVector<SDNode*, 128> Worklist;
+ SmallVector<SDNode *, 128> Worklist;
Worklist.push_back(CurDAG->getRoot().getNode());
Added.insert(CurDAG->getRoot().getNode());
@@ -922,9 +923,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->NewNodesMustHaveLegalTypes = false;
#ifndef NDEBUG
- MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
- FilterDAGBasicBlockName ==
- FuncInfo->MBB->getBasicBlock()->getName());
+ MatchFilterBB =
+ (FilterDAGBasicBlockName.empty() ||
+ FilterDAGBasicBlockName == FuncInfo->MBB->getBasicBlock()->getName());
#endif
#ifdef NDEBUG
if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewDAGCombineLT ||
@@ -1175,7 +1176,7 @@ class ISelUpdater : public SelectionDAG::DAGUpdateListener {
public:
ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
- : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
+ : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
/// NodeDeleted - Handle nodes deleted from the graph. If the node being
/// deleted is the current ISelPosition node, update ISelPosition.
@@ -1267,7 +1268,7 @@ void SelectionDAGISel::DoInstructionSelection() {
// a reference to the root node, preventing it from being deleted,
// and tracking any changes of the root.
HandleSDNode Dummy(CurDAG->getRoot());
- SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
+ SelectionDAG::allnodes_iterator ISelPosition(CurDAG->getRoot().getNode());
++ISelPosition;
// Make sure that ISelPosition gets properly updated when nodes are deleted
@@ -1339,8 +1340,8 @@ void SelectionDAGISel::DoInstructionSelection() {
ActionVT = Node->getValueType(0);
break;
}
- if (TLI->getOperationAction(Node->getOpcode(), ActionVT)
- == TargetLowering::Expand)
+ if (TLI->getOperationAction(Node->getOpcode(), ActionVT) ==
+ TargetLowering::Expand)
Node = CurDAG->mutateStrictFPToFP(Node);
}
@@ -1439,8 +1440,7 @@ bool SelectionDAGISel::PrepareEHLandingPad() {
MCSymbol *Label = MF->addLandingPad(MBB);
const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
- BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
- .addSym(Label);
+ BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II).addSym(Label);
// If the unwinder does not preserve all registers, ensure that the
// function marks the clobbered registers as used.
@@ -1476,6 +1476,11 @@ void SelectionDAGISel::reportIPToStateForBlocks(MachineFunction *MF) {
if (BB->getFirstMayFaultInst()) {
// Report IP range only for blocks with Faulty inst
auto MBBb = MBB.getFirstNonPHI();
+
+ // Avoids attempting to dereference a sentintel which fails an assert
+ if (MBBb == MBB.instr_end())
+ continue;
+
MachineInstr *MIb = &*MBBb;
if (MIb->isTerminator())
continue;
@@ -1627,7 +1632,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
}
- ReversePostOrderTraversal<const Function*> RPOT(&Fn);
+ ReversePostOrderTraversal<const Function *> RPOT(&Fn);
// Lower arguments up front. An RPO iteration always visits the entry block
// first.
@@ -1651,8 +1656,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
++NumFastIselFailLowerArguments;
OptimizationRemarkMissed R("sdagisel", "FastISelFailure",
- Fn.getSubprogram(),
- &Fn.getEntryBlock());
+ Fn.getSubprogram(), &Fn.getEntryBlock());
R << "FastISel didn't lower all arguments: "
<< ore::NV("Prototype", Fn.getFunctionType());
reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 1);
@@ -1919,8 +1923,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
SDB->SPDescriptor.resetPerFunctionState();
}
-void
-SelectionDAGISel::FinishBasicBlock() {
+void SelectionDAGISel::FinishBasicBlock() {
LLVM_DEBUG(dbgs() << "Total amount of phi nodes to update: "
<< FuncInfo->PHINodesToUpdate.size() << "\n";
for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e;
@@ -1947,8 +1950,7 @@ SelectionDAGISel::FinishBasicBlock() {
// Add load and check to the basicblock.
FuncInfo->MBB = ParentMBB;
- FuncInfo->InsertPt =
- findSplitPointForStackProtector(ParentMBB, *TII);
+ FuncInfo->InsertPt = findSplitPointForStackProtector(ParentMBB, *TII);
SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
CurDAG->setRoot(SDB->getRoot());
SDB->clear();
@@ -1970,8 +1972,7 @@ SelectionDAGISel::FinishBasicBlock() {
findSplitPointForStackProtector(ParentMBB, *TII);
// Splice the terminator of ParentMBB into SuccessMBB.
- SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
- SplitPoint,
+ SuccessMBB->splice(SuccessMBB->end(), ParentMBB, SplitPoint,
ParentMBB->end());
// Add compare/jump on neq/jump to the parent BB.
@@ -2067,11 +2068,11 @@ SelectionDAGISel::FinishBasicBlock() {
PHI.addReg(P.second).addMBB(BTB.Parent);
if (!BTB.ContiguousRange) {
PHI.addReg(P.second).addMBB(BTB.Cases.back().ThisBB);
- }
+ }
}
// One of "cases" BB.
for (const SwitchCG::BitTestCase &BT : BTB.Cases) {
- MachineBasicBlock* cBB = BT.ThisBB;
+ MachineBasicBlock *cBB = BT.ThisBB;
if (cBB->isSuccessor(PHIBB))
PHI.addReg(P.second).addMBB(cBB);
}
@@ -2106,8 +2107,8 @@ SelectionDAGISel::FinishBasicBlock() {
CodeGenAndEmitDAG();
// Update PHI Nodes
- for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
- pi != pe; ++pi) {
+ for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); pi != pe;
+ ++pi) {
MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
MachineBasicBlock *PHIBB = PHI->getParent();
assert(PHI->isPHI() &&
@@ -2115,7 +2116,7 @@ SelectionDAGISel::FinishBasicBlock() {
// "default" BB. We can go there only from header BB.
if (PHIBB == SDB->SL->JTCases[i].second.Default)
PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
- .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
+ .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
// JT BB. Just iterate over successors here
if (FuncInfo->MBB->isSuccessor(PHIBB))
PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
@@ -2156,12 +2157,12 @@ SelectionDAGISel::FinishBasicBlock() {
// FuncInfo->MBB may have been removed from the CFG if a branch was
// constant folded.
if (ThisBB->isSuccessor(FuncInfo->MBB)) {
- for (MachineBasicBlock::iterator
- MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
+ for (MachineBasicBlock::iterator MBBI = FuncInfo->MBB->begin(),
+ MBBE = FuncInfo->MBB->end();
MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
MachineInstrBuilder PHI(*MF, MBBI);
// This value for this PHI node is recorded in PHINodesToUpdate.
- for (unsigned pn = 0; ; ++pn) {
+ for (unsigned pn = 0;; ++pn) {
assert(pn != FuncInfo->PHINodesToUpdate.size() &&
"Didn't find PHI entry!");
if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
@@ -2267,7 +2268,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
unsigned i = InlineAsm::Op_FirstOperand, e = Ops.size();
if (Ops[e - 1].getValueType() == MVT::Glue)
- --e; // Don't process a glue operand if it is here.
+ --e; // Don't process a glue operand if it is here.
while (i != e) {
InlineAsm::Flag Flags(Ops[i]->getAsZExtVal());
@@ -2323,7 +2324,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
/// SDNode.
///
static SDNode *findGlueUse(SDNode *N) {
- unsigned FlagResNo = N->getNumValues()-1;
+ unsigned FlagResNo = N->getNumValues() - 1;
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
SDUse &Use = I.getUse();
if (Use.getResNo() == FlagResNo)
@@ -2433,13 +2434,13 @@ bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
// If the node has glue, walk down the graph to the "lowest" node in the
// glueged set.
- EVT VT = Root->getValueType(Root->getNumValues()-1);
+ EVT VT = Root->getValueType(Root->getNumValues() - 1);
while (VT == MVT::Glue) {
SDNode *GU = findGlueUse(Root);
if (!GU)
break;
Root = GU;
- VT = Root->getValueType(Root->getNumValues()-1);
+ VT = Root->getValueType(Root->getNumValues() - 1);
// If our query node has a glue result with a use, we've walked up it. If
// the user (which has already been selected) has a chain or indirectly uses
@@ -2471,11 +2472,10 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
EVT VT = Op->getValueType(0);
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
- Register Reg =
- TLI->getRegisterByName(RegStr->getString().data(), Ty,
- CurDAG->getMachineFunction());
- SDValue New = CurDAG->getCopyFromReg(
- Op->getOperand(0), dl, Reg, Op->getValueType(0));
+ Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
+ CurDAG->getMachineFunction());
+ SDValue New =
+ CurDAG->getCopyFromReg(Op->getOperand(0), dl, Reg, Op->getValueType(0));
New->setNodeId(-1);
ReplaceUses(Op, New.getNode());
CurDAG->RemoveDeadNode(Op);
@@ -2491,8 +2491,8 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
CurDAG->getMachineFunction());
- SDValue New = CurDAG->getCopyToReg(
- Op->getOperand(0), dl, Reg, Op->getOperand(2));
+ SDValue New =
+ CurDAG->getCopyToReg(Op->getOperand(0), dl, Reg, Op->getOperand(2));
New->setNodeId(-1);
ReplaceUses(Op, New.getNode());
CurDAG->RemoveDeadNode(Op);
@@ -2645,13 +2645,13 @@ void SelectionDAGISel::Select_PATCHPOINT(SDNode *N) {
LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
assert(Val >= 128 && "Not a VBR");
- Val &= 127; // Remove first vbr bit.
+ Val &= 127; // Remove first vbr bit.
unsigned Shift = 7;
uint64_t NextBits;
do {
NextBits = MatcherTable[Idx++];
- Val |= (NextBits&127) << Shift;
+ Val |= (NextBits & 127) << Shift;
Shift += 7;
} while (NextBits & 128);
@@ -2681,7 +2681,7 @@ void SelectionDAGISel::Select_JUMP_TABLE_DEBUG_INFO(SDNode *N) {
void SelectionDAGISel::UpdateChains(
SDNode *NodeToMatch, SDValue InputChain,
SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo) {
- SmallVector<SDNode*, 4> NowDeadNodes;
+ SmallVector<SDNode *, 4> NowDeadNodes;
// Now that all the normal results are replaced, we replace the chain and
// glue results if present.
@@ -2705,9 +2705,9 @@ void SelectionDAGISel::UpdateChains(
if (ChainNode == NodeToMatch && isMorphNodeTo)
continue;
- SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
+ SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues() - 1);
if (ChainVal.getValueType() == MVT::Glue)
- ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
+ ChainVal = ChainVal.getValue(ChainVal->getNumValues() - 2);
assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
SelectionDAG::DAGNodeDeletedListener NDL(
*CurDAG, [&](SDNode *N, SDNode *E) {
@@ -2737,7 +2737,7 @@ void SelectionDAGISel::UpdateChains(
/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
/// be used as the input node chain for the generated nodes.
static SDValue
-HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
+HandleMergeInputChains(SmallVectorImpl<SDNode *> &ChainNodesMatched,
SelectionDAG *CurDAG) {
SmallPtrSet<const SDNode *, 16> Visited;
@@ -2796,9 +2796,9 @@ HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
}
/// MorphNode - Handle morphing a node in place for the selector.
-SDNode *SelectionDAGISel::
-MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
- ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
+SDNode *SelectionDAGISel::MorphNode(SDNode *Node, unsigned TargetOpc,
+ SDVTList VTList, ArrayRef<SDValue> Ops,
+ unsigned EmitNodeInfo) {
// It is possible we're using MorphNodeTo to replace a node with no
// normal results with one that has a normal result (or we could be
// adding a chain) and the input could have glue and chains as well.
@@ -2808,13 +2808,13 @@ MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
int OldGlueResultNo = -1, OldChainResultNo = -1;
unsigned NTMNumResults = Node->getNumValues();
- if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
- OldGlueResultNo = NTMNumResults-1;
+ if (Node->getValueType(NTMNumResults - 1) == MVT::Glue) {
+ OldGlueResultNo = NTMNumResults - 1;
if (NTMNumResults != 1 &&
- Node->getValueType(NTMNumResults-2) == MVT::Other)
- OldChainResultNo = NTMNumResults-2;
- } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
- OldChainResultNo = NTMNumResults-1;
+ Node->getValueType(NTMNumResults - 2) == MVT::Other)
+ OldChainResultNo = NTMNumResults - 2;
+ } else if (Node->getValueType(NTMNumResults - 1) == MVT::Other)
+ OldChainResultNo = NTMNumResults - 1;
// Call the underlying SelectionDAG routine to do the transmogrification. Note
// that this deletes operands of the old node that become dead.
@@ -2872,7 +2872,7 @@ LLVM_ATTRIBUTE_ALWAYS_INLINE static bool CheckChildSame(
const SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes,
unsigned ChildNo) {
if (ChildNo >= N.getNumOperands())
- return false; // Match fails if out of range child #.
+ return false; // Match fails if out of range child #.
return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
RecordedNodes);
}
@@ -2984,7 +2984,7 @@ LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
SDValue N, unsigned ChildNo) {
if (ChildNo >= N.getNumOperands())
- return false; // Match fails if out of range child #.
+ return false; // Match fails if out of range child #.
return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
}
@@ -2995,7 +2995,8 @@ CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (N->getOpcode() != ISD::AND) return false;
+ if (N->getOpcode() != ISD::AND)
+ return false;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
@@ -3008,7 +3009,8 @@ CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (N->getOpcode() != ISD::OR) return false;
+ if (N->getOpcode() != ISD::OR)
+ return false;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
@@ -3020,16 +3022,15 @@ CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
/// known to pass, set Result=false and return the MatcherIndex to continue
/// with. If the current predicate is unknown, set Result=false and return the
/// MatcherIndex to continue with.
-static unsigned IsPredicateKnownToFail(const unsigned char *Table,
- unsigned Index, SDValue N,
- bool &Result,
- const SelectionDAGISel &SDISel,
- SmallVectorImpl<std::pair<SDValue, SDNode*>> &RecordedNodes) {
+static unsigned IsPredicateKnownToFail(
+ const unsigned char *Table, unsigned Index, SDValue N, bool &Result,
+ const SelectionDAGISel &SDISel,
+ SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes) {
unsigned Opcode = Table[Index++];
switch (Opcode) {
default:
Result = false;
- return Index-1; // Could not evaluate this predicate.
+ return Index - 1; // Could not evaluate this predicate.
case SelectionDAGISel::OPC_CheckSame:
Result = !::CheckSame(Table, Index, N, RecordedNodes);
return Index;
@@ -3038,7 +3039,8 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
case SelectionDAGISel::OPC_CheckChild2Same:
case SelectionDAGISel::OPC_CheckChild3Same:
Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
- Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
+ Table[Index - 1] -
+ SelectionDAGISel::OPC_CheckChild0Same);
return Index;
case SelectionDAGISel::OPC_CheckPatternPredicate:
case SelectionDAGISel::OPC_CheckPatternPredicate0:
@@ -3151,7 +3153,8 @@ static unsigned IsPredicateKnownToFail(const unsigned char *Table,
case SelectionDAGISel::OPC_CheckChild3Integer:
case SelectionDAGISel::OPC_CheckChild4Integer:
Result = !::CheckChildInteger(Table, Index, N,
- Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
+ Table[Index - 1] -
+ SelectionDAGISel::OPC_CheckChild0Integer);
return Index;
case SelectionDAGISel::OPC_CheckAndImm:
Result = !::CheckAndImm(Table, Index, N, SDISel);
@@ -3188,8 +3191,7 @@ struct MatchScope {
/// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
/// change the DAG while matching. X86 addressing mode matcher is an example
/// for this.
-class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
-{
+class MatchStateUpdater : public SelectionDAG::DAGUpdateListener {
SDNode **NodeToMatch;
SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes;
SmallVectorImpl<MatchScope> &MatchScopes;
@@ -3235,7 +3237,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
switch (NodeToMatch->getOpcode()) {
default:
break;
- case ISD::EntryToken: // These nodes remain the same.
+ case ISD::EntryToken: // These nodes remain the same.
case ISD::BasicBlock:
case ISD::Register:
case ISD::RegisterMask:
@@ -3326,11 +3328,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// RecordedNodes - This is the set of nodes that have been recorded by the
// state machine. The second value is the parent of the node, or null if the
// root is recorded.
- SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
+ SmallVector<std::pair<SDValue, SDNode *>, 8> RecordedNodes;
// MatchedMemRefs - This is the set of MemRef's we've seen in the input
// pattern.
- SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
+ SmallVector<MachineMemOperand *, 2> MatchedMemRefs;
// These are the current input chain and glue for use when generating nodes.
// Various Emit operations change these. For example, emitting a copytoreg
@@ -3341,7 +3343,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// chains, the OPC_EmitMergeInputChains operation is emitted which indicates
// which ones they are. The result is captured into this list so that we can
// update the chain results when the pattern is complete.
- SmallVector<SDNode*, 3> ChainNodesMatched;
+ SmallVector<SDNode *, 3> ChainNodesMatched;
LLVM_DEBUG(dbgs() << "ISEL: Starting pattern match\n");
@@ -3367,13 +3369,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
unsigned CaseSize = MatcherTable[Idx++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
- if (CaseSize == 0) break;
+ if (CaseSize == 0)
+ break;
// Get the opcode, add the index to the table.
uint16_t Opc = MatcherTable[Idx++];
Opc |= static_cast<uint16_t>(MatcherTable[Idx++]) << 8;
if (Opc >= OpcodeOffset.size())
- OpcodeOffset.resize((Opc+1)*2);
+ OpcodeOffset.resize((Opc + 1) * 2);
OpcodeOffset[Opc] = Idx;
Idx += CaseSize;
}
@@ -3409,7 +3412,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
break;
}
- FailIndex = MatcherIndex+NumToSkip;
+ FailIndex = MatcherIndex + NumToSkip;
unsigned MatcherIndexOfPredicate = MatcherIndex;
(void)MatcherIndexOfPredicate; // silence warning.
@@ -3435,7 +3438,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If the whole scope failed to match, bail.
- if (FailIndex == 0) break;
+ if (FailIndex == 0)
+ break;
// Push a MatchScope which indicates where to go if the first child fails
// to match.
@@ -3454,21 +3458,25 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// Remember this node, it may end up being an operand in the pattern.
SDNode *Parent = nullptr;
if (NodeStack.size() > 1)
- Parent = NodeStack[NodeStack.size()-2].getNode();
+ Parent = NodeStack[NodeStack.size() - 2].getNode();
RecordedNodes.push_back(std::make_pair(N, Parent));
continue;
}
- case OPC_RecordChild0: case OPC_RecordChild1:
- case OPC_RecordChild2: case OPC_RecordChild3:
- case OPC_RecordChild4: case OPC_RecordChild5:
- case OPC_RecordChild6: case OPC_RecordChild7: {
- unsigned ChildNo = Opcode-OPC_RecordChild0;
+ case OPC_RecordChild0:
+ case OPC_RecordChild1:
+ case OPC_RecordChild2:
+ case OPC_RecordChild3:
+ case OPC_RecordChild4:
+ case OPC_RecordChild5:
+ case OPC_RecordChild6:
+ case OPC_RecordChild7: {
+ unsigned ChildNo = Opcode - OPC_RecordChild0;
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
- RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
- N.getNode()));
+ RecordedNodes.push_back(
+ std::make_pair(N->getOperand(ChildNo), N.getNode()));
continue;
}
case OPC_RecordMemRef:
@@ -3484,26 +3492,30 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_CaptureGlueInput:
// If the current node has an input glue, capture it in InputGlue.
if (N->getNumOperands() != 0 &&
- N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
- InputGlue = N->getOperand(N->getNumOperands()-1);
+ N->getOperand(N->getNumOperands() - 1).getValueType() == MVT::Glue)
+ InputGlue = N->getOperand(N->getNumOperands() - 1);
continue;
case OPC_MoveChild: {
unsigned ChildNo = MatcherTable[MatcherIndex++];
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
N = N.getOperand(ChildNo);
NodeStack.push_back(N);
continue;
}
- case OPC_MoveChild0: case OPC_MoveChild1:
- case OPC_MoveChild2: case OPC_MoveChild3:
- case OPC_MoveChild4: case OPC_MoveChild5:
- case OPC_MoveChild6: case OPC_MoveChild7: {
- unsigned ChildNo = Opcode-OPC_MoveChild0;
+ case OPC_MoveChild0:
+ case OPC_MoveChild1:
+ case OPC_MoveChild2:
+ case OPC_MoveChild3:
+ case OPC_MoveChild4:
+ case OPC_MoveChild5:
+ case OPC_MoveChild6:
+ case OPC_MoveChild7: {
+ unsigned ChildNo = Opcode - OPC_MoveChild0;
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
N = N.getOperand(ChildNo);
NodeStack.push_back(N);
continue;
@@ -3540,13 +3552,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
case OPC_CheckSame:
- if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
+ if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes))
+ break;
continue;
- case OPC_CheckChild0Same: case OPC_CheckChild1Same:
- case OPC_CheckChild2Same: case OPC_CheckChild3Same:
+ case OPC_CheckChild0Same:
+ case OPC_CheckChild1Same:
+ case OPC_CheckChild2Same:
+ case OPC_CheckChild3Same:
if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
- Opcode-OPC_CheckChild0Same))
+ Opcode - OPC_CheckChild0Same))
break;
continue;
@@ -3617,7 +3632,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
case OPC_CheckOpcode:
- if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
+ if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode()))
+ break;
continue;
case OPC_CheckType:
@@ -3649,14 +3665,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_SwitchOpcode: {
unsigned CurNodeOpcode = N.getOpcode();
- unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
+ unsigned SwitchStart = MatcherIndex - 1;
+ (void)SwitchStart;
unsigned CaseSize;
while (true) {
// Get the size of this case.
CaseSize = MatcherTable[MatcherIndex++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
- if (CaseSize == 0) break;
+ if (CaseSize == 0)
+ break;
uint16_t Opc = MatcherTable[MatcherIndex++];
Opc |= static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
@@ -3670,7 +3688,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If no cases matched, bail out.
- if (CaseSize == 0) break;
+ if (CaseSize == 0)
+ break;
// Otherwise, execute the case we found.
LLVM_DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart << " to "
@@ -3680,14 +3699,16 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_SwitchType: {
MVT CurNodeVT = N.getSimpleValueType();
- unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
+ unsigned SwitchStart = MatcherIndex - 1;
+ (void)SwitchStart;
unsigned CaseSize;
while (true) {
// Get the size of this case.
CaseSize = MatcherTable[MatcherIndex++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
- if (CaseSize == 0) break;
+ if (CaseSize == 0)
+ break;
MVT CaseVT = getSimpleVT(MatcherTable, MatcherIndex);
if (CaseVT == MVT::iPTR)
@@ -3702,12 +3723,12 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If no cases matched, bail out.
- if (CaseSize == 0) break;
+ if (CaseSize == 0)
+ break;
// Otherwise, execute the case we found.
- LLVM_DEBUG(dbgs() << " TypeSwitch[" << CurNodeVT
- << "] from " << SwitchStart << " to " << MatcherIndex
- << '\n');
+ LLVM_DEBUG(dbgs() << " TypeSwitch[" << CurNodeVT << "] from "
+ << SwitchStart << " to " << MatcherIndex << '\n');
continue;
}
case OPC_CheckChild0Type:
@@ -3753,10 +3774,12 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
case OPC_CheckCondCode:
- if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
+ if (!::CheckCondCode(MatcherTable, MatcherIndex, N))
+ break;
continue;
case OPC_CheckChild2CondCode:
- if (!::CheckChild2CondCode(MatcherTable, MatcherIndex, N)) break;
+ if (!::CheckChild2CondCode(MatcherTable, MatcherIndex, N))
+ break;
continue;
case OPC_CheckValueType:
if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
@@ -3764,19 +3787,25 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
break;
continue;
case OPC_CheckInteger:
- if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
+ if (!::CheckInteger(MatcherTable, MatcherIndex, N))
+ break;
continue;
- case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
- case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
+ case OPC_CheckChild0Integer:
+ case OPC_CheckChild1Integer:
+ case OPC_CheckChild2Integer:
+ case OPC_CheckChild3Integer:
case OPC_CheckChild4Integer:
if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
- Opcode-OPC_CheckChild0Integer)) break;
+ Opcode - OPC_CheckChild0Integer))
+ break;
continue;
case OPC_CheckAndImm:
- if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
+ if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this))
+ break;
continue;
case OPC_CheckOrImm:
- if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
+ if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this))
+ break;
continue;
case OPC_CheckImmAllOnesV:
if (!ISD::isConstantSplatVectorAllOnes(N.getNode()))
@@ -3792,7 +3821,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// Verify that all intermediate nodes between the root and this one have
// a single use (ignoring chains, which are handled in UpdateChains).
bool HasMultipleUses = false;
- for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) {
+ for (unsigned i = 1, e = NodeStack.size() - 1; i != e; ++i) {
unsigned NNonChainUses = 0;
SDNode *NS = NodeStack[i].getNode();
for (auto UI = NS->use_begin(), UE = NS->use_end(); UI != UE; ++UI)
@@ -3801,17 +3830,19 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
HasMultipleUses = true;
break;
}
- if (HasMultipleUses) break;
+ if (HasMultipleUses)
+ break;
}
- if (HasMultipleUses) break;
+ if (HasMultipleUses)
+ break;
// Check to see that the target thinks this is profitable to fold and that
// we can fold it without inducing cycles in the graph.
- if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
+ if (!IsProfitableToFold(N, NodeStack[NodeStack.size() - 2].getNode(),
NodeToMatch) ||
- !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
+ !IsLegalToFold(N, NodeStack[NodeStack.size() - 2].getNode(),
NodeToMatch, OptLevel,
- true/*We validate our own chains*/))
+ true /*We validate our own chains*/))
break;
continue;
@@ -3880,8 +3911,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
MVT::SimpleValueType VT = getSimpleVT(MatcherTable, MatcherIndex);
unsigned RegNo = MatcherTable[MatcherIndex++];
RegNo |= MatcherTable[MatcherIndex++] << 8;
- RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
- CurDAG->getRegister(RegNo, VT), nullptr));
+ RecordedNodes.push_back(std::pair<SDValue, SDNode *>(
+ CurDAG->getRegister(RegNo, VT), nullptr));
continue;
}
@@ -3902,11 +3933,13 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
SDValue Imm = RecordedNodes[RecNo].first;
if (Imm->getOpcode() == ISD::Constant) {
- const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
+ const ConstantInt *Val =
+ cast<ConstantSDNode>(Imm)->getConstantIntValue();
Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch),
Imm.getValueType());
} else if (Imm->getOpcode() == ISD::ConstantFP) {
- const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
+ const ConstantFP *Val =
+ cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
Imm = CurDAG->getTargetConstantFP(*Val, SDLoc(NodeToMatch),
Imm.getValueType());
}
@@ -3915,9 +3948,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
- case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
- case OPC_EmitMergeInputChains1_1: // OPC_EmitMergeInputChains, 1, 1
- case OPC_EmitMergeInputChains1_2: { // OPC_EmitMergeInputChains, 1, 2
+ case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
+ case OPC_EmitMergeInputChains1_1: // OPC_EmitMergeInputChains, 1, 1
+ case OPC_EmitMergeInputChains1_2: { // OPC_EmitMergeInputChains, 1, 2
// These are space-optimized forms of OPC_EmitMergeInputChains.
assert(!InputChain.getNode() &&
"EmitMergeInputChains should be the first chain producing node");
@@ -3943,7 +3976,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
if (!InputChain.getNode())
- break; // Failed to merge.
+ break; // Failed to merge.
continue;
}
@@ -3987,7 +4020,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
if (!InputChain.getNode())
- break; // Failed to merge.
+ break; // Failed to merge.
continue;
}
@@ -4014,9 +4047,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!InputChain.getNode())
InputChain = CurDAG->getEntryNode();
- InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
- DestPhysReg, RecordedNodes[RecNo].first,
- InputGlue);
+ InputChain =
+ CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), DestPhysReg,
+ RecordedNodes[RecNo].first, InputGlue);
InputGlue = InputChain.getValue(1);
continue;
@@ -4027,7 +4060,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
unsigned RecNo = MatcherTable[MatcherIndex++];
assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
- RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
+ RecordedNodes.push_back(std::pair<SDValue, SDNode *>(Res, nullptr));
continue;
}
case OPC_Coverage: {
@@ -4160,7 +4193,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
i != e; ++i) {
SDValue V = NodeToMatch->getOperand(i);
- if (V.getValueType() == MVT::Glue) break;
+ if (V.getValueType() == MVT::Glue)
+ break;
Ops.push_back(V);
}
}
@@ -4188,28 +4222,29 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!IsMorphNodeTo) {
// If this is a normal EmitNode command, just create the new node and
// add the results to the RecordedNodes list.
- Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
- VTList, Ops);
+ Res =
+ CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), VTList, Ops);
// Add all the non-glue/non-chain results to the RecordedNodes list.
for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
- if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
- RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
- nullptr));
+ if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue)
+ break;
+ RecordedNodes.push_back(
+ std::pair<SDValue, SDNode *>(SDValue(Res, i), nullptr));
}
} else {
assert(NodeToMatch->getOpcode() != ISD::DELETED_NODE &&
"NodeToMatch was removed partway through selection");
- SelectionDAG::DAGNodeDeletedListener NDL(*CurDAG, [&](SDNode *N,
- SDNode *E) {
- CurDAG->salvageDebugInfo(*N);
- auto &Chain = ChainNodesMatched;
- assert((!E || !is_contained(Chain, N)) &&
- "Chain node replaced during MorphNode");
- llvm::erase(Chain, N);
- });
- Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList,
- Ops, EmitNodeInfo));
+ SelectionDAG::DAGNodeDeletedListener NDL(
+ *CurDAG, [&](SDNode *N, SDNode *E) {
+ CurDAG->salvageDebugInfo(*N);
+ auto &Chain = ChainNodesMatched;
+ assert((!E || !is_contained(Chain, N)) &&
+ "Chain node replaced during MorphNode");
+ llvm::erase(Chain, N);
+ });
+ Res = cast<MachineSDNode>(
+ MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo));
}
// Set the NoFPExcept flag when no original matched node could
@@ -4223,11 +4258,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// If the node had chain/glue results, update our notion of the current
// chain and glue.
if (EmitNodeInfo & OPFL_GlueOutput) {
- InputGlue = SDValue(Res, VTs.size()-1);
+ InputGlue = SDValue(Res, VTs.size() - 1);
if (EmitNodeInfo & OPFL_Chain)
- InputChain = SDValue(Res, VTs.size()-2);
+ InputChain = SDValue(Res, VTs.size() - 2);
} else if (EmitNodeInfo & OPFL_Chain)
- InputChain = SDValue(Res, VTs.size()-1);
+ InputChain = SDValue(Res, VTs.size() - 1);
// If the OPFL_MemRefs glue is set on this node, slap all of the
// accumulated memrefs onto it.
@@ -4364,7 +4399,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// If we have another child in this scope to match, update FailIndex and
// try it.
if (NumToSkip != 0) {
- LastScope.FailIndex = MatcherIndex+NumToSkip;
+ LastScope.FailIndex = MatcherIndex + NumToSkip;
break;
}
>From 21b4087a90d38de71e57281e4cf79c0507e23b77 Mon Sep 17 00:00:00 2001
From: R-Goc <ryszardgoc at gmail.com>
Date: Tue, 3 Sep 2024 12:11:44 +0200
Subject: [PATCH 2/4] format previous commit
---
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 562 +++++++++---------
1 file changed, 266 insertions(+), 296 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 22a4cb04d717ef..4a6ecc4ea0bb44 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -121,8 +121,7 @@ STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on");
STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected");
STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel");
STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG");
-STATISTIC(NumDAGIselRetries,
- "Number of times dag isel has to try another path");
+STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path");
STATISTIC(NumEntryBlocks, "Number of entry blocks encountered");
STATISTIC(NumFastIselFailLowerArguments,
"Number of entry blocks where fast isel failed to lower arguments");
@@ -140,22 +139,23 @@ static cl::opt<bool> EnableFastISelFallbackReport(
cl::desc("Emit a diagnostic when \"fast\" instruction selection "
"falls back to SelectionDAG."));
-static cl::opt<bool> UseMBPI("use-mbpi",
- cl::desc("use Machine Branch Probability Info"),
- cl::init(true), cl::Hidden);
+static cl::opt<bool>
+UseMBPI("use-mbpi",
+ cl::desc("use Machine Branch Probability Info"),
+ cl::init(true), cl::Hidden);
#ifndef NDEBUG
-static cl::opt<std::string> FilterDAGBasicBlockName(
- "filter-view-dags", cl::Hidden,
- cl::desc("Only display the basic block whose name "
- "matches this for all view-*-dags options"));
+static cl::opt<std::string>
+FilterDAGBasicBlockName("filter-view-dags", cl::Hidden,
+ cl::desc("Only display the basic block whose name "
+ "matches this for all view-*-dags options"));
+static cl::opt<bool>
+ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before the first "
+ "dag combine pass"));
static cl::opt<bool>
- ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before the first "
- "dag combine pass"));
-static cl::opt<bool> ViewLegalizeTypesDAGs(
- "view-legalize-types-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before legalize types"));
+ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before legalize types"));
static cl::opt<bool>
ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before the post "
@@ -164,18 +164,18 @@ static cl::opt<bool>
ViewLegalizeDAGs("view-legalize-dags", cl::Hidden,
cl::desc("Pop up a window to show dags before legalize"));
static cl::opt<bool>
- ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
- cl::desc("Pop up a window to show dags before the second "
- "dag combine pass"));
-static cl::opt<bool> ViewISelDAGs(
- "view-isel-dags", cl::Hidden,
- cl::desc("Pop up a window to show isel dags as they are selected"));
-static cl::opt<bool> ViewSchedDAGs(
- "view-sched-dags", cl::Hidden,
- cl::desc("Pop up a window to show sched dags as they are processed"));
-static cl::opt<bool> ViewSUnitDAGs(
- "view-sunit-dags", cl::Hidden,
- cl::desc("Pop up a window to show SUnit dags after they are processed"));
+ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden,
+ cl::desc("Pop up a window to show dags before the second "
+ "dag combine pass"));
+static cl::opt<bool>
+ViewISelDAGs("view-isel-dags", cl::Hidden,
+ cl::desc("Pop up a window to show isel dags as they are selected"));
+static cl::opt<bool>
+ViewSchedDAGs("view-sched-dags", cl::Hidden,
+ cl::desc("Pop up a window to show sched dags as they are processed"));
+static cl::opt<bool>
+ViewSUnitDAGs("view-sunit-dags", cl::Hidden,
+ cl::desc("Pop up a window to show SUnit dags after they are processed"));
#else
static const bool ViewDAGCombine1 = false, ViewLegalizeTypesDAGs = false,
ViewDAGCombineLT = false, ViewLegalizeDAGs = false,
@@ -193,9 +193,7 @@ static const bool ViewDAGCombine1 = false, ViewLegalizeTypesDAGs = false,
} \
} while (false)
#else
-#define ISEL_DUMP(X) \
- do { \
- } while (false)
+#define ISEL_DUMP(X) do { } while (false)
#endif
//===---------------------------------------------------------------------===//
@@ -213,13 +211,14 @@ MachinePassRegistry<RegisterScheduler::FunctionPassCtor>
//===---------------------------------------------------------------------===//
static cl::opt<RegisterScheduler::FunctionPassCtor, false,
RegisterPassParser<RegisterScheduler>>
- ISHeuristic("pre-RA-sched", cl::init(&createDefaultScheduler), cl::Hidden,
- cl::desc("Instruction schedulers available (before register"
- " allocation):"));
+ISHeuristic("pre-RA-sched",
+ cl::init(&createDefaultScheduler), cl::Hidden,
+ cl::desc("Instruction schedulers available (before register"
+ " allocation):"));
static RegisterScheduler
- defaultListDAGScheduler("default", "Best scheduler for the target",
- createDefaultScheduler);
+defaultListDAGScheduler("default", "Best scheduler for the target",
+ createDefaultScheduler);
static bool dontUseFastISelFor(const Function &Fn) {
// Don't enable FastISel for functions with swiftasync Arguments.
@@ -233,82 +232,83 @@ static bool dontUseFastISelFor(const Function &Fn) {
namespace llvm {
-//===--------------------------------------------------------------------===//
-/// This class is used by SelectionDAGISel to temporarily override
-/// the optimization level on a per-function basis.
-class OptLevelChanger {
- SelectionDAGISel &IS;
- CodeGenOptLevel SavedOptLevel;
- bool SavedFastISel;
+ //===--------------------------------------------------------------------===//
+ /// This class is used by SelectionDAGISel to temporarily override
+ /// the optimization level on a per-function basis.
+ class OptLevelChanger {
+ SelectionDAGISel &IS;
+ CodeGenOptLevel SavedOptLevel;
+ bool SavedFastISel;
+
+ public:
+ OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
+ : IS(ISel) {
+ SavedOptLevel = IS.OptLevel;
+ SavedFastISel = IS.TM.Options.EnableFastISel;
+ if (NewOptLevel != SavedOptLevel) {
+ IS.OptLevel = NewOptLevel;
+ IS.TM.setOptLevel(NewOptLevel);
+ LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
+ << IS.MF->getFunction().getName() << "\n");
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel)
+ << " ; After: -O" << static_cast<int>(NewOptLevel)
+ << "\n");
+ if (NewOptLevel == CodeGenOptLevel::None)
+ IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
+ }
+ if (dontUseFastISelFor(IS.MF->getFunction()))
+ IS.TM.setFastISel(false);
+ LLVM_DEBUG(
+ dbgs() << "\tFastISel is "
+ << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
+ << "\n");
+ }
-public:
- OptLevelChanger(SelectionDAGISel &ISel, CodeGenOptLevel NewOptLevel)
- : IS(ISel) {
- SavedOptLevel = IS.OptLevel;
- SavedFastISel = IS.TM.Options.EnableFastISel;
- if (NewOptLevel != SavedOptLevel) {
- IS.OptLevel = NewOptLevel;
- IS.TM.setOptLevel(NewOptLevel);
- LLVM_DEBUG(dbgs() << "\nChanging optimization level for Function "
+ ~OptLevelChanger() {
+ if (IS.OptLevel == SavedOptLevel)
+ return;
+ LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
<< IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(SavedOptLevel)
- << " ; After: -O" << static_cast<int>(NewOptLevel)
- << "\n");
- if (NewOptLevel == CodeGenOptLevel::None)
- IS.TM.setFastISel(IS.TM.getO0WantsFastISel());
+ LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
+ << " ; After: -O" << static_cast<int>(SavedOptLevel) << "\n");
+ IS.OptLevel = SavedOptLevel;
+ IS.TM.setOptLevel(SavedOptLevel);
+ IS.TM.setFastISel(SavedFastISel);
}
- if (dontUseFastISelFor(IS.MF->getFunction()))
- IS.TM.setFastISel(false);
- LLVM_DEBUG(dbgs() << "\tFastISel is "
- << (IS.TM.Options.EnableFastISel ? "enabled" : "disabled")
- << "\n");
- }
+ };
- ~OptLevelChanger() {
- if (IS.OptLevel == SavedOptLevel)
- return;
- LLVM_DEBUG(dbgs() << "\nRestoring optimization level for Function "
- << IS.MF->getFunction().getName() << "\n");
- LLVM_DEBUG(dbgs() << "\tBefore: -O" << static_cast<int>(IS.OptLevel)
- << " ; After: -O" << static_cast<int>(SavedOptLevel)
- << "\n");
- IS.OptLevel = SavedOptLevel;
- IS.TM.setOptLevel(SavedOptLevel);
- IS.TM.setFastISel(SavedFastISel);
- }
-};
+ //===--------------------------------------------------------------------===//
+ /// createDefaultScheduler - This creates an instruction scheduler appropriate
+ /// for the target.
+ ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
+ CodeGenOptLevel OptLevel) {
+ const TargetLowering *TLI = IS->TLI;
+ const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
+
+ // Try first to see if the Target has its own way of selecting a scheduler
+ if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
+ return SchedulerCtor(IS, OptLevel);
+ }
-//===--------------------------------------------------------------------===//
-/// createDefaultScheduler - This creates an instruction scheduler appropriate
-/// for the target.
-ScheduleDAGSDNodes *createDefaultScheduler(SelectionDAGISel *IS,
- CodeGenOptLevel OptLevel) {
- const TargetLowering *TLI = IS->TLI;
- const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
-
- // Try first to see if the Target has its own way of selecting a scheduler
- if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
- return SchedulerCtor(IS, OptLevel);
+ if (OptLevel == CodeGenOptLevel::None ||
+ (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
+ TLI->getSchedulingPreference() == Sched::Source)
+ return createSourceListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::RegPressure)
+ return createBURRListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Hybrid)
+ return createHybridListDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::VLIW)
+ return createVLIWDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Fast)
+ return createFastDAGScheduler(IS, OptLevel);
+ if (TLI->getSchedulingPreference() == Sched::Linearize)
+ return createDAGLinearizer(IS, OptLevel);
+ assert(TLI->getSchedulingPreference() == Sched::ILP &&
+ "Unknown sched type!");
+ return createILPListDAGScheduler(IS, OptLevel);
}
- if (OptLevel == CodeGenOptLevel::None ||
- (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
- TLI->getSchedulingPreference() == Sched::Source)
- return createSourceListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::RegPressure)
- return createBURRListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Hybrid)
- return createHybridListDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::VLIW)
- return createVLIWDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Fast)
- return createFastDAGScheduler(IS, OptLevel);
- if (TLI->getSchedulingPreference() == Sched::Linearize)
- return createDAGLinearizer(IS, OptLevel);
- assert(TLI->getSchedulingPreference() == Sched::ILP && "Unknown sched type!");
- return createILPListDAGScheduler(IS, OptLevel);
-}
-
} // end namespace llvm
MachineBasicBlock *
@@ -316,8 +316,8 @@ TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *MBB) const {
#ifndef NDEBUG
dbgs() << "If a target marks an instruction with "
- "'usesCustomInserter', it must implement "
- "TargetLowering::EmitInstrWithCustomInserter!\n";
+ "'usesCustomInserter', it must implement "
+ "TargetLowering::EmitInstrWithCustomInserter!\n";
#endif
llvm_unreachable(nullptr);
}
@@ -396,7 +396,7 @@ SelectionDAGISel::~SelectionDAGISel() {
void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
CodeGenOptLevel OptLevel = Selector->OptLevel;
if (OptLevel != CodeGenOptLevel::None)
- AU.addRequired<AAResultsWrapperPass>();
+ AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<GCModuleInfo>();
AU.addRequired<StackProtector>();
AU.addPreserved<GCModuleInfo>();
@@ -406,14 +406,14 @@ void SelectionDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
#endif
AU.addRequired<AssumptionCacheTracker>();
if (UseMBPI && OptLevel != CodeGenOptLevel::None)
- AU.addRequired<BranchProbabilityInfoWrapperPass>();
+ AU.addRequired<BranchProbabilityInfoWrapperPass>();
AU.addRequired<ProfileSummaryInfoWrapperPass>();
// AssignmentTrackingAnalysis only runs if assignment tracking is enabled for
// the module.
AU.addRequired<AssignmentTrackingAnalysis>();
AU.addPreserved<AssignmentTrackingAnalysis>();
if (OptLevel != CodeGenOptLevel::None)
- LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
+ LazyBlockFrequencyInfoPass::getLazyBFIAnalysisUsage(AU);
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -658,7 +658,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
// Insert copies in the entry block and the return blocks.
if (FuncInfo->SplitCSR) {
- SmallVector<MachineBasicBlock *, 4> Returns;
+ SmallVector<MachineBasicBlock*, 4> Returns;
// Collect all the return blocks.
for (MachineBasicBlock &MBB : mf) {
if (!MBB.succ_empty())
@@ -857,8 +857,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
// Lower the instructions. If a call is emitted as a tail call, cease emitting
// nodes for this block. If an instruction is elided, don't emit it, but do
// handle any debug-info attached to it.
- for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall;
- ++I) {
+ for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) {
if (!ElidedArgCopyInstrs.count(&*I))
SDB->visit(*I);
else
@@ -877,7 +876,7 @@ void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
void SelectionDAGISel::ComputeLiveOutVRegInfo() {
SmallPtrSet<SDNode *, 16> Added;
- SmallVector<SDNode *, 128> Worklist;
+ SmallVector<SDNode*, 128> Worklist;
Worklist.push_back(CurDAG->getRoot().getNode());
Added.insert(CurDAG->getRoot().getNode());
@@ -923,9 +922,9 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
CurDAG->NewNodesMustHaveLegalTypes = false;
#ifndef NDEBUG
- MatchFilterBB =
- (FilterDAGBasicBlockName.empty() ||
- FilterDAGBasicBlockName == FuncInfo->MBB->getBasicBlock()->getName());
+ MatchFilterBB = (FilterDAGBasicBlockName.empty() ||
+ FilterDAGBasicBlockName ==
+ FuncInfo->MBB->getBasicBlock()->getName());
#endif
#ifdef NDEBUG
if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewDAGCombineLT ||
@@ -1176,7 +1175,7 @@ class ISelUpdater : public SelectionDAG::DAGUpdateListener {
public:
ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp)
- : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
+ : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {}
/// NodeDeleted - Handle nodes deleted from the graph. If the node being
/// deleted is the current ISelPosition node, update ISelPosition.
@@ -1268,7 +1267,7 @@ void SelectionDAGISel::DoInstructionSelection() {
// a reference to the root node, preventing it from being deleted,
// and tracking any changes of the root.
HandleSDNode Dummy(CurDAG->getRoot());
- SelectionDAG::allnodes_iterator ISelPosition(CurDAG->getRoot().getNode());
+ SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode());
++ISelPosition;
// Make sure that ISelPosition gets properly updated when nodes are deleted
@@ -1340,8 +1339,8 @@ void SelectionDAGISel::DoInstructionSelection() {
ActionVT = Node->getValueType(0);
break;
}
- if (TLI->getOperationAction(Node->getOpcode(), ActionVT) ==
- TargetLowering::Expand)
+ if (TLI->getOperationAction(Node->getOpcode(), ActionVT)
+ == TargetLowering::Expand)
Node = CurDAG->mutateStrictFPToFP(Node);
}
@@ -1440,7 +1439,8 @@ bool SelectionDAGISel::PrepareEHLandingPad() {
MCSymbol *Label = MF->addLandingPad(MBB);
const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL);
- BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II).addSym(Label);
+ BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
+ .addSym(Label);
// If the unwinder does not preserve all registers, ensure that the
// function marks the clobbered registers as used.
@@ -1632,7 +1632,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
FastIS = TLI->createFastISel(*FuncInfo, LibInfo);
}
- ReversePostOrderTraversal<const Function *> RPOT(&Fn);
+ ReversePostOrderTraversal<const Function*> RPOT(&Fn);
// Lower arguments up front. An RPO iteration always visits the entry block
// first.
@@ -1656,7 +1656,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
++NumFastIselFailLowerArguments;
OptimizationRemarkMissed R("sdagisel", "FastISelFailure",
- Fn.getSubprogram(), &Fn.getEntryBlock());
+ Fn.getSubprogram(),
+ &Fn.getEntryBlock());
R << "FastISel didn't lower all arguments: "
<< ore::NV("Prototype", Fn.getFunctionType());
reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 1);
@@ -1923,7 +1924,8 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
SDB->SPDescriptor.resetPerFunctionState();
}
-void SelectionDAGISel::FinishBasicBlock() {
+void
+SelectionDAGISel::FinishBasicBlock() {
LLVM_DEBUG(dbgs() << "Total amount of phi nodes to update: "
<< FuncInfo->PHINodesToUpdate.size() << "\n";
for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e;
@@ -1950,7 +1952,8 @@ void SelectionDAGISel::FinishBasicBlock() {
// Add load and check to the basicblock.
FuncInfo->MBB = ParentMBB;
- FuncInfo->InsertPt = findSplitPointForStackProtector(ParentMBB, *TII);
+ FuncInfo->InsertPt =
+ findSplitPointForStackProtector(ParentMBB, *TII);
SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB);
CurDAG->setRoot(SDB->getRoot());
SDB->clear();
@@ -1972,7 +1975,8 @@ void SelectionDAGISel::FinishBasicBlock() {
findSplitPointForStackProtector(ParentMBB, *TII);
// Splice the terminator of ParentMBB into SuccessMBB.
- SuccessMBB->splice(SuccessMBB->end(), ParentMBB, SplitPoint,
+ SuccessMBB->splice(SuccessMBB->end(), ParentMBB,
+ SplitPoint,
ParentMBB->end());
// Add compare/jump on neq/jump to the parent BB.
@@ -2068,11 +2072,11 @@ void SelectionDAGISel::FinishBasicBlock() {
PHI.addReg(P.second).addMBB(BTB.Parent);
if (!BTB.ContiguousRange) {
PHI.addReg(P.second).addMBB(BTB.Cases.back().ThisBB);
- }
+ }
}
// One of "cases" BB.
for (const SwitchCG::BitTestCase &BT : BTB.Cases) {
- MachineBasicBlock *cBB = BT.ThisBB;
+ MachineBasicBlock* cBB = BT.ThisBB;
if (cBB->isSuccessor(PHIBB))
PHI.addReg(P.second).addMBB(cBB);
}
@@ -2107,8 +2111,8 @@ void SelectionDAGISel::FinishBasicBlock() {
CodeGenAndEmitDAG();
// Update PHI Nodes
- for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); pi != pe;
- ++pi) {
+ for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
+ pi != pe; ++pi) {
MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
MachineBasicBlock *PHIBB = PHI->getParent();
assert(PHI->isPHI() &&
@@ -2116,7 +2120,7 @@ void SelectionDAGISel::FinishBasicBlock() {
// "default" BB. We can go there only from header BB.
if (PHIBB == SDB->SL->JTCases[i].second.Default)
PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
- .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
+ .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
// JT BB. Just iterate over successors here
if (FuncInfo->MBB->isSuccessor(PHIBB))
PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
@@ -2157,12 +2161,12 @@ void SelectionDAGISel::FinishBasicBlock() {
// FuncInfo->MBB may have been removed from the CFG if a branch was
// constant folded.
if (ThisBB->isSuccessor(FuncInfo->MBB)) {
- for (MachineBasicBlock::iterator MBBI = FuncInfo->MBB->begin(),
- MBBE = FuncInfo->MBB->end();
+ for (MachineBasicBlock::iterator
+ MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end();
MBBI != MBBE && MBBI->isPHI(); ++MBBI) {
MachineInstrBuilder PHI(*MF, MBBI);
// This value for this PHI node is recorded in PHINodesToUpdate.
- for (unsigned pn = 0;; ++pn) {
+ for (unsigned pn = 0; ; ++pn) {
assert(pn != FuncInfo->PHINodesToUpdate.size() &&
"Didn't find PHI entry!");
if (FuncInfo->PHINodesToUpdate[pn].first == PHI) {
@@ -2268,7 +2272,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
unsigned i = InlineAsm::Op_FirstOperand, e = Ops.size();
if (Ops[e - 1].getValueType() == MVT::Glue)
- --e; // Don't process a glue operand if it is here.
+ --e; // Don't process a glue operand if it is here.
while (i != e) {
InlineAsm::Flag Flags(Ops[i]->getAsZExtVal());
@@ -2324,7 +2328,7 @@ void SelectionDAGISel::SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops,
/// SDNode.
///
static SDNode *findGlueUse(SDNode *N) {
- unsigned FlagResNo = N->getNumValues() - 1;
+ unsigned FlagResNo = N->getNumValues()-1;
for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) {
SDUse &Use = I.getUse();
if (Use.getResNo() == FlagResNo)
@@ -2434,13 +2438,13 @@ bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root,
// If the node has glue, walk down the graph to the "lowest" node in the
// glueged set.
- EVT VT = Root->getValueType(Root->getNumValues() - 1);
+ EVT VT = Root->getValueType(Root->getNumValues()-1);
while (VT == MVT::Glue) {
SDNode *GU = findGlueUse(Root);
if (!GU)
break;
Root = GU;
- VT = Root->getValueType(Root->getNumValues() - 1);
+ VT = Root->getValueType(Root->getNumValues()-1);
// If our query node has a glue result with a use, we've walked up it. If
// the user (which has already been selected) has a chain or indirectly uses
@@ -2472,10 +2476,11 @@ void SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) {
EVT VT = Op->getValueType(0);
LLT Ty = VT.isSimple() ? getLLTForMVT(VT.getSimpleVT()) : LLT();
- Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
- CurDAG->getMachineFunction());
- SDValue New =
- CurDAG->getCopyFromReg(Op->getOperand(0), dl, Reg, Op->getValueType(0));
+ Register Reg =
+ TLI->getRegisterByName(RegStr->getString().data(), Ty,
+ CurDAG->getMachineFunction());
+ SDValue New = CurDAG->getCopyFromReg(
+ Op->getOperand(0), dl, Reg, Op->getValueType(0));
New->setNodeId(-1);
ReplaceUses(Op, New.getNode());
CurDAG->RemoveDeadNode(Op);
@@ -2491,8 +2496,8 @@ void SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) {
Register Reg = TLI->getRegisterByName(RegStr->getString().data(), Ty,
CurDAG->getMachineFunction());
- SDValue New =
- CurDAG->getCopyToReg(Op->getOperand(0), dl, Reg, Op->getOperand(2));
+ SDValue New = CurDAG->getCopyToReg(
+ Op->getOperand(0), dl, Reg, Op->getOperand(2));
New->setNodeId(-1);
ReplaceUses(Op, New.getNode());
CurDAG->RemoveDeadNode(Op);
@@ -2645,13 +2650,13 @@ void SelectionDAGISel::Select_PATCHPOINT(SDNode *N) {
LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t
GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) {
assert(Val >= 128 && "Not a VBR");
- Val &= 127; // Remove first vbr bit.
+ Val &= 127; // Remove first vbr bit.
unsigned Shift = 7;
uint64_t NextBits;
do {
NextBits = MatcherTable[Idx++];
- Val |= (NextBits & 127) << Shift;
+ Val |= (NextBits&127) << Shift;
Shift += 7;
} while (NextBits & 128);
@@ -2681,7 +2686,7 @@ void SelectionDAGISel::Select_JUMP_TABLE_DEBUG_INFO(SDNode *N) {
void SelectionDAGISel::UpdateChains(
SDNode *NodeToMatch, SDValue InputChain,
SmallVectorImpl<SDNode *> &ChainNodesMatched, bool isMorphNodeTo) {
- SmallVector<SDNode *, 4> NowDeadNodes;
+ SmallVector<SDNode*, 4> NowDeadNodes;
// Now that all the normal results are replaced, we replace the chain and
// glue results if present.
@@ -2705,9 +2710,9 @@ void SelectionDAGISel::UpdateChains(
if (ChainNode == NodeToMatch && isMorphNodeTo)
continue;
- SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues() - 1);
+ SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1);
if (ChainVal.getValueType() == MVT::Glue)
- ChainVal = ChainVal.getValue(ChainVal->getNumValues() - 2);
+ ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2);
assert(ChainVal.getValueType() == MVT::Other && "Not a chain?");
SelectionDAG::DAGNodeDeletedListener NDL(
*CurDAG, [&](SDNode *N, SDNode *E) {
@@ -2737,7 +2742,7 @@ void SelectionDAGISel::UpdateChains(
/// induce cycles in the DAG) and if so, creating a TokenFactor node. that will
/// be used as the input node chain for the generated nodes.
static SDValue
-HandleMergeInputChains(SmallVectorImpl<SDNode *> &ChainNodesMatched,
+HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched,
SelectionDAG *CurDAG) {
SmallPtrSet<const SDNode *, 16> Visited;
@@ -2796,9 +2801,9 @@ HandleMergeInputChains(SmallVectorImpl<SDNode *> &ChainNodesMatched,
}
/// MorphNode - Handle morphing a node in place for the selector.
-SDNode *SelectionDAGISel::MorphNode(SDNode *Node, unsigned TargetOpc,
- SDVTList VTList, ArrayRef<SDValue> Ops,
- unsigned EmitNodeInfo) {
+SDNode *SelectionDAGISel::
+MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList,
+ ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) {
// It is possible we're using MorphNodeTo to replace a node with no
// normal results with one that has a normal result (or we could be
// adding a chain) and the input could have glue and chains as well.
@@ -2808,13 +2813,13 @@ SDNode *SelectionDAGISel::MorphNode(SDNode *Node, unsigned TargetOpc,
int OldGlueResultNo = -1, OldChainResultNo = -1;
unsigned NTMNumResults = Node->getNumValues();
- if (Node->getValueType(NTMNumResults - 1) == MVT::Glue) {
- OldGlueResultNo = NTMNumResults - 1;
+ if (Node->getValueType(NTMNumResults-1) == MVT::Glue) {
+ OldGlueResultNo = NTMNumResults-1;
if (NTMNumResults != 1 &&
- Node->getValueType(NTMNumResults - 2) == MVT::Other)
- OldChainResultNo = NTMNumResults - 2;
- } else if (Node->getValueType(NTMNumResults - 1) == MVT::Other)
- OldChainResultNo = NTMNumResults - 1;
+ Node->getValueType(NTMNumResults-2) == MVT::Other)
+ OldChainResultNo = NTMNumResults-2;
+ } else if (Node->getValueType(NTMNumResults-1) == MVT::Other)
+ OldChainResultNo = NTMNumResults-1;
// Call the underlying SelectionDAG routine to do the transmogrification. Note
// that this deletes operands of the old node that become dead.
@@ -2872,7 +2877,7 @@ LLVM_ATTRIBUTE_ALWAYS_INLINE static bool CheckChildSame(
const SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes,
unsigned ChildNo) {
if (ChildNo >= N.getNumOperands())
- return false; // Match fails if out of range child #.
+ return false; // Match fails if out of range child #.
return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo),
RecordedNodes);
}
@@ -2984,7 +2989,7 @@ LLVM_ATTRIBUTE_ALWAYS_INLINE static bool
CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex,
SDValue N, unsigned ChildNo) {
if (ChildNo >= N.getNumOperands())
- return false; // Match fails if out of range child #.
+ return false; // Match fails if out of range child #.
return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo));
}
@@ -2995,8 +3000,7 @@ CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex,
if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (N->getOpcode() != ISD::AND)
- return false;
+ if (N->getOpcode() != ISD::AND) return false;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
@@ -3009,8 +3013,7 @@ CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
if (Val & 128)
Val = GetVBR(Val, MatcherTable, MatcherIndex);
- if (N->getOpcode() != ISD::OR)
- return false;
+ if (N->getOpcode() != ISD::OR) return false;
ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
@@ -3022,15 +3025,16 @@ CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, SDValue N,
/// known to pass, set Result=false and return the MatcherIndex to continue
/// with. If the current predicate is unknown, set Result=false and return the
/// MatcherIndex to continue with.
-static unsigned IsPredicateKnownToFail(
- const unsigned char *Table, unsigned Index, SDValue N, bool &Result,
- const SelectionDAGISel &SDISel,
- SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes) {
+static unsigned IsPredicateKnownToFail(const unsigned char *Table,
+ unsigned Index, SDValue N,
+ bool &Result,
+ const SelectionDAGISel &SDISel,
+ SmallVectorImpl<std::pair<SDValue, SDNode*>> &RecordedNodes) {
unsigned Opcode = Table[Index++];
switch (Opcode) {
default:
Result = false;
- return Index - 1; // Could not evaluate this predicate.
+ return Index-1; // Could not evaluate this predicate.
case SelectionDAGISel::OPC_CheckSame:
Result = !::CheckSame(Table, Index, N, RecordedNodes);
return Index;
@@ -3039,8 +3043,7 @@ static unsigned IsPredicateKnownToFail(
case SelectionDAGISel::OPC_CheckChild2Same:
case SelectionDAGISel::OPC_CheckChild3Same:
Result = !::CheckChildSame(Table, Index, N, RecordedNodes,
- Table[Index - 1] -
- SelectionDAGISel::OPC_CheckChild0Same);
+ Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same);
return Index;
case SelectionDAGISel::OPC_CheckPatternPredicate:
case SelectionDAGISel::OPC_CheckPatternPredicate0:
@@ -3153,8 +3156,7 @@ static unsigned IsPredicateKnownToFail(
case SelectionDAGISel::OPC_CheckChild3Integer:
case SelectionDAGISel::OPC_CheckChild4Integer:
Result = !::CheckChildInteger(Table, Index, N,
- Table[Index - 1] -
- SelectionDAGISel::OPC_CheckChild0Integer);
+ Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer);
return Index;
case SelectionDAGISel::OPC_CheckAndImm:
Result = !::CheckAndImm(Table, Index, N, SDISel);
@@ -3191,7 +3193,8 @@ struct MatchScope {
/// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to
/// change the DAG while matching. X86 addressing mode matcher is an example
/// for this.
-class MatchStateUpdater : public SelectionDAG::DAGUpdateListener {
+class MatchStateUpdater : public SelectionDAG::DAGUpdateListener
+{
SDNode **NodeToMatch;
SmallVectorImpl<std::pair<SDValue, SDNode *>> &RecordedNodes;
SmallVectorImpl<MatchScope> &MatchScopes;
@@ -3237,7 +3240,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
switch (NodeToMatch->getOpcode()) {
default:
break;
- case ISD::EntryToken: // These nodes remain the same.
+ case ISD::EntryToken: // These nodes remain the same.
case ISD::BasicBlock:
case ISD::Register:
case ISD::RegisterMask:
@@ -3328,11 +3331,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// RecordedNodes - This is the set of nodes that have been recorded by the
// state machine. The second value is the parent of the node, or null if the
// root is recorded.
- SmallVector<std::pair<SDValue, SDNode *>, 8> RecordedNodes;
+ SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes;
// MatchedMemRefs - This is the set of MemRef's we've seen in the input
// pattern.
- SmallVector<MachineMemOperand *, 2> MatchedMemRefs;
+ SmallVector<MachineMemOperand*, 2> MatchedMemRefs;
// These are the current input chain and glue for use when generating nodes.
// Various Emit operations change these. For example, emitting a copytoreg
@@ -3343,7 +3346,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// chains, the OPC_EmitMergeInputChains operation is emitted which indicates
// which ones they are. The result is captured into this list so that we can
// update the chain results when the pattern is complete.
- SmallVector<SDNode *, 3> ChainNodesMatched;
+ SmallVector<SDNode*, 3> ChainNodesMatched;
LLVM_DEBUG(dbgs() << "ISEL: Starting pattern match\n");
@@ -3369,14 +3372,13 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
unsigned CaseSize = MatcherTable[Idx++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, Idx);
- if (CaseSize == 0)
- break;
+ if (CaseSize == 0) break;
// Get the opcode, add the index to the table.
uint16_t Opc = MatcherTable[Idx++];
Opc |= static_cast<uint16_t>(MatcherTable[Idx++]) << 8;
if (Opc >= OpcodeOffset.size())
- OpcodeOffset.resize((Opc + 1) * 2);
+ OpcodeOffset.resize((Opc+1)*2);
OpcodeOffset[Opc] = Idx;
Idx += CaseSize;
}
@@ -3412,7 +3414,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
break;
}
- FailIndex = MatcherIndex + NumToSkip;
+ FailIndex = MatcherIndex+NumToSkip;
unsigned MatcherIndexOfPredicate = MatcherIndex;
(void)MatcherIndexOfPredicate; // silence warning.
@@ -3438,8 +3440,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If the whole scope failed to match, bail.
- if (FailIndex == 0)
- break;
+ if (FailIndex == 0) break;
// Push a MatchScope which indicates where to go if the first child fails
// to match.
@@ -3458,25 +3459,21 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// Remember this node, it may end up being an operand in the pattern.
SDNode *Parent = nullptr;
if (NodeStack.size() > 1)
- Parent = NodeStack[NodeStack.size() - 2].getNode();
+ Parent = NodeStack[NodeStack.size()-2].getNode();
RecordedNodes.push_back(std::make_pair(N, Parent));
continue;
}
- case OPC_RecordChild0:
- case OPC_RecordChild1:
- case OPC_RecordChild2:
- case OPC_RecordChild3:
- case OPC_RecordChild4:
- case OPC_RecordChild5:
- case OPC_RecordChild6:
- case OPC_RecordChild7: {
- unsigned ChildNo = Opcode - OPC_RecordChild0;
+ case OPC_RecordChild0: case OPC_RecordChild1:
+ case OPC_RecordChild2: case OPC_RecordChild3:
+ case OPC_RecordChild4: case OPC_RecordChild5:
+ case OPC_RecordChild6: case OPC_RecordChild7: {
+ unsigned ChildNo = Opcode-OPC_RecordChild0;
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
- RecordedNodes.push_back(
- std::make_pair(N->getOperand(ChildNo), N.getNode()));
+ RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo),
+ N.getNode()));
continue;
}
case OPC_RecordMemRef:
@@ -3492,30 +3489,26 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_CaptureGlueInput:
// If the current node has an input glue, capture it in InputGlue.
if (N->getNumOperands() != 0 &&
- N->getOperand(N->getNumOperands() - 1).getValueType() == MVT::Glue)
- InputGlue = N->getOperand(N->getNumOperands() - 1);
+ N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue)
+ InputGlue = N->getOperand(N->getNumOperands()-1);
continue;
case OPC_MoveChild: {
unsigned ChildNo = MatcherTable[MatcherIndex++];
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
N = N.getOperand(ChildNo);
NodeStack.push_back(N);
continue;
}
- case OPC_MoveChild0:
- case OPC_MoveChild1:
- case OPC_MoveChild2:
- case OPC_MoveChild3:
- case OPC_MoveChild4:
- case OPC_MoveChild5:
- case OPC_MoveChild6:
- case OPC_MoveChild7: {
- unsigned ChildNo = Opcode - OPC_MoveChild0;
+ case OPC_MoveChild0: case OPC_MoveChild1:
+ case OPC_MoveChild2: case OPC_MoveChild3:
+ case OPC_MoveChild4: case OPC_MoveChild5:
+ case OPC_MoveChild6: case OPC_MoveChild7: {
+ unsigned ChildNo = Opcode-OPC_MoveChild0;
if (ChildNo >= N.getNumOperands())
- break; // Match fails if out of range child #.
+ break; // Match fails if out of range child #.
N = N.getOperand(ChildNo);
NodeStack.push_back(N);
continue;
@@ -3552,16 +3545,13 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
case OPC_CheckSame:
- if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes))
- break;
+ if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break;
continue;
- case OPC_CheckChild0Same:
- case OPC_CheckChild1Same:
- case OPC_CheckChild2Same:
- case OPC_CheckChild3Same:
+ case OPC_CheckChild0Same: case OPC_CheckChild1Same:
+ case OPC_CheckChild2Same: case OPC_CheckChild3Same:
if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes,
- Opcode - OPC_CheckChild0Same))
+ Opcode-OPC_CheckChild0Same))
break;
continue;
@@ -3632,8 +3622,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
case OPC_CheckOpcode:
- if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode()))
- break;
+ if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break;
continue;
case OPC_CheckType:
@@ -3665,16 +3654,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_SwitchOpcode: {
unsigned CurNodeOpcode = N.getOpcode();
- unsigned SwitchStart = MatcherIndex - 1;
- (void)SwitchStart;
+ unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
unsigned CaseSize;
while (true) {
// Get the size of this case.
CaseSize = MatcherTable[MatcherIndex++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
- if (CaseSize == 0)
- break;
+ if (CaseSize == 0) break;
uint16_t Opc = MatcherTable[MatcherIndex++];
Opc |= static_cast<uint16_t>(MatcherTable[MatcherIndex++]) << 8;
@@ -3688,8 +3675,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If no cases matched, bail out.
- if (CaseSize == 0)
- break;
+ if (CaseSize == 0) break;
// Otherwise, execute the case we found.
LLVM_DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart << " to "
@@ -3699,16 +3685,14 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
case OPC_SwitchType: {
MVT CurNodeVT = N.getSimpleValueType();
- unsigned SwitchStart = MatcherIndex - 1;
- (void)SwitchStart;
+ unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart;
unsigned CaseSize;
while (true) {
// Get the size of this case.
CaseSize = MatcherTable[MatcherIndex++];
if (CaseSize & 128)
CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex);
- if (CaseSize == 0)
- break;
+ if (CaseSize == 0) break;
MVT CaseVT = getSimpleVT(MatcherTable, MatcherIndex);
if (CaseVT == MVT::iPTR)
@@ -3723,12 +3707,12 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
}
// If no cases matched, bail out.
- if (CaseSize == 0)
- break;
+ if (CaseSize == 0) break;
// Otherwise, execute the case we found.
- LLVM_DEBUG(dbgs() << " TypeSwitch[" << CurNodeVT << "] from "
- << SwitchStart << " to " << MatcherIndex << '\n');
+ LLVM_DEBUG(dbgs() << " TypeSwitch[" << CurNodeVT
+ << "] from " << SwitchStart << " to " << MatcherIndex
+ << '\n');
continue;
}
case OPC_CheckChild0Type:
@@ -3774,12 +3758,10 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
case OPC_CheckCondCode:
- if (!::CheckCondCode(MatcherTable, MatcherIndex, N))
- break;
+ if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break;
continue;
case OPC_CheckChild2CondCode:
- if (!::CheckChild2CondCode(MatcherTable, MatcherIndex, N))
- break;
+ if (!::CheckChild2CondCode(MatcherTable, MatcherIndex, N)) break;
continue;
case OPC_CheckValueType:
if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI,
@@ -3787,25 +3769,19 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
break;
continue;
case OPC_CheckInteger:
- if (!::CheckInteger(MatcherTable, MatcherIndex, N))
- break;
+ if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break;
continue;
- case OPC_CheckChild0Integer:
- case OPC_CheckChild1Integer:
- case OPC_CheckChild2Integer:
- case OPC_CheckChild3Integer:
+ case OPC_CheckChild0Integer: case OPC_CheckChild1Integer:
+ case OPC_CheckChild2Integer: case OPC_CheckChild3Integer:
case OPC_CheckChild4Integer:
if (!::CheckChildInteger(MatcherTable, MatcherIndex, N,
- Opcode - OPC_CheckChild0Integer))
- break;
+ Opcode-OPC_CheckChild0Integer)) break;
continue;
case OPC_CheckAndImm:
- if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this))
- break;
+ if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break;
continue;
case OPC_CheckOrImm:
- if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this))
- break;
+ if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break;
continue;
case OPC_CheckImmAllOnesV:
if (!ISD::isConstantSplatVectorAllOnes(N.getNode()))
@@ -3821,7 +3797,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// Verify that all intermediate nodes between the root and this one have
// a single use (ignoring chains, which are handled in UpdateChains).
bool HasMultipleUses = false;
- for (unsigned i = 1, e = NodeStack.size() - 1; i != e; ++i) {
+ for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) {
unsigned NNonChainUses = 0;
SDNode *NS = NodeStack[i].getNode();
for (auto UI = NS->use_begin(), UE = NS->use_end(); UI != UE; ++UI)
@@ -3830,19 +3806,17 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
HasMultipleUses = true;
break;
}
- if (HasMultipleUses)
- break;
+ if (HasMultipleUses) break;
}
- if (HasMultipleUses)
- break;
+ if (HasMultipleUses) break;
// Check to see that the target thinks this is profitable to fold and that
// we can fold it without inducing cycles in the graph.
- if (!IsProfitableToFold(N, NodeStack[NodeStack.size() - 2].getNode(),
+ if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(),
NodeToMatch) ||
- !IsLegalToFold(N, NodeStack[NodeStack.size() - 2].getNode(),
+ !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(),
NodeToMatch, OptLevel,
- true /*We validate our own chains*/))
+ true/*We validate our own chains*/))
break;
continue;
@@ -3911,8 +3885,8 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
MVT::SimpleValueType VT = getSimpleVT(MatcherTable, MatcherIndex);
unsigned RegNo = MatcherTable[MatcherIndex++];
RegNo |= MatcherTable[MatcherIndex++] << 8;
- RecordedNodes.push_back(std::pair<SDValue, SDNode *>(
- CurDAG->getRegister(RegNo, VT), nullptr));
+ RecordedNodes.push_back(std::pair<SDValue, SDNode*>(
+ CurDAG->getRegister(RegNo, VT), nullptr));
continue;
}
@@ -3933,13 +3907,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
SDValue Imm = RecordedNodes[RecNo].first;
if (Imm->getOpcode() == ISD::Constant) {
- const ConstantInt *Val =
- cast<ConstantSDNode>(Imm)->getConstantIntValue();
+ const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch),
Imm.getValueType());
} else if (Imm->getOpcode() == ISD::ConstantFP) {
- const ConstantFP *Val =
- cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
+ const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue();
Imm = CurDAG->getTargetConstantFP(*Val, SDLoc(NodeToMatch),
Imm.getValueType());
}
@@ -3948,9 +3920,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
continue;
}
- case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
- case OPC_EmitMergeInputChains1_1: // OPC_EmitMergeInputChains, 1, 1
- case OPC_EmitMergeInputChains1_2: { // OPC_EmitMergeInputChains, 1, 2
+ case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0
+ case OPC_EmitMergeInputChains1_1: // OPC_EmitMergeInputChains, 1, 1
+ case OPC_EmitMergeInputChains1_2: { // OPC_EmitMergeInputChains, 1, 2
// These are space-optimized forms of OPC_EmitMergeInputChains.
assert(!InputChain.getNode() &&
"EmitMergeInputChains should be the first chain producing node");
@@ -3976,7 +3948,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
if (!InputChain.getNode())
- break; // Failed to merge.
+ break; // Failed to merge.
continue;
}
@@ -4020,7 +3992,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG);
if (!InputChain.getNode())
- break; // Failed to merge.
+ break; // Failed to merge.
continue;
}
@@ -4047,9 +4019,9 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!InputChain.getNode())
InputChain = CurDAG->getEntryNode();
- InputChain =
- CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), DestPhysReg,
- RecordedNodes[RecNo].first, InputGlue);
+ InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch),
+ DestPhysReg, RecordedNodes[RecNo].first,
+ InputGlue);
InputGlue = InputChain.getValue(1);
continue;
@@ -4060,7 +4032,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
unsigned RecNo = MatcherTable[MatcherIndex++];
assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm");
SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo);
- RecordedNodes.push_back(std::pair<SDValue, SDNode *>(Res, nullptr));
+ RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr));
continue;
}
case OPC_Coverage: {
@@ -4193,8 +4165,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands();
i != e; ++i) {
SDValue V = NodeToMatch->getOperand(i);
- if (V.getValueType() == MVT::Glue)
- break;
+ if (V.getValueType() == MVT::Glue) break;
Ops.push_back(V);
}
}
@@ -4222,29 +4193,28 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
if (!IsMorphNodeTo) {
// If this is a normal EmitNode command, just create the new node and
// add the results to the RecordedNodes list.
- Res =
- CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), VTList, Ops);
+ Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch),
+ VTList, Ops);
// Add all the non-glue/non-chain results to the RecordedNodes list.
for (unsigned i = 0, e = VTs.size(); i != e; ++i) {
- if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue)
- break;
- RecordedNodes.push_back(
- std::pair<SDValue, SDNode *>(SDValue(Res, i), nullptr));
+ if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break;
+ RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i),
+ nullptr));
}
} else {
assert(NodeToMatch->getOpcode() != ISD::DELETED_NODE &&
"NodeToMatch was removed partway through selection");
- SelectionDAG::DAGNodeDeletedListener NDL(
- *CurDAG, [&](SDNode *N, SDNode *E) {
- CurDAG->salvageDebugInfo(*N);
- auto &Chain = ChainNodesMatched;
- assert((!E || !is_contained(Chain, N)) &&
- "Chain node replaced during MorphNode");
- llvm::erase(Chain, N);
- });
- Res = cast<MachineSDNode>(
- MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo));
+ SelectionDAG::DAGNodeDeletedListener NDL(*CurDAG, [&](SDNode *N,
+ SDNode *E) {
+ CurDAG->salvageDebugInfo(*N);
+ auto &Chain = ChainNodesMatched;
+ assert((!E || !is_contained(Chain, N)) &&
+ "Chain node replaced during MorphNode");
+ llvm::erase(Chain, N);
+ });
+ Res = cast<MachineSDNode>(MorphNode(NodeToMatch, TargetOpc, VTList,
+ Ops, EmitNodeInfo));
}
// Set the NoFPExcept flag when no original matched node could
@@ -4258,11 +4228,11 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// If the node had chain/glue results, update our notion of the current
// chain and glue.
if (EmitNodeInfo & OPFL_GlueOutput) {
- InputGlue = SDValue(Res, VTs.size() - 1);
+ InputGlue = SDValue(Res, VTs.size()-1);
if (EmitNodeInfo & OPFL_Chain)
- InputChain = SDValue(Res, VTs.size() - 2);
+ InputChain = SDValue(Res, VTs.size()-2);
} else if (EmitNodeInfo & OPFL_Chain)
- InputChain = SDValue(Res, VTs.size() - 1);
+ InputChain = SDValue(Res, VTs.size()-1);
// If the OPFL_MemRefs glue is set on this node, slap all of the
// accumulated memrefs onto it.
@@ -4399,7 +4369,7 @@ void SelectionDAGISel::SelectCodeCommon(SDNode *NodeToMatch,
// If we have another child in this scope to match, update FailIndex and
// try it.
if (NumToSkip != 0) {
- LastScope.FailIndex = MatcherIndex + NumToSkip;
+ LastScope.FailIndex = MatcherIndex+NumToSkip;
break;
}
@@ -4464,4 +4434,4 @@ void SelectionDAGISel::CannotYetSelect(SDNode *N) {
Msg << "unknown intrinsic #" << iid;
}
report_fatal_error(Twine(msg));
-}
+}
\ No newline at end of file
>From f96874288769292f937efd76ee47a6e44f910b4e Mon Sep 17 00:00:00 2001
From: R-Goc <ryszardgoc at gmail.com>
Date: Wed, 4 Sep 2024 00:49:55 +0200
Subject: [PATCH 3/4] Add test for EHa crash
---
llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
diff --git a/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll b/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
new file mode 100644
index 00000000000000..fa71e2dd8ded18
--- /dev/null
+++ b/llvm/test/CodeGen/WinEH/wineh-empty-seh-scope.ll
@@ -0,0 +1,14 @@
+; RUN: llc -mtriple=x86_64-pc-windows-msvc19.41.34120 %s
+
+define void @foo() personality ptr @__CxxFrameHandler3 {
+ call void @llvm.seh.scope.begin()
+ unreachable
+}
+
+declare i32 @__CxxFrameHandler3(...)
+
+declare void @llvm.seh.scope.begin()
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 2, !"eh-asynch", i32 1}
>From 05bb993f7e1a34d3a33b1915b25888835cbdf231 Mon Sep 17 00:00:00 2001
From: R-Goc <ryszardgoc at gmail.com>
Date: Wed, 4 Sep 2024 14:25:28 +0200
Subject: [PATCH 4/4] Use end() instead of instr_end() and add newline
---
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 4a6ecc4ea0bb44..4a70f5d58e98f1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1478,7 +1478,7 @@ void SelectionDAGISel::reportIPToStateForBlocks(MachineFunction *MF) {
auto MBBb = MBB.getFirstNonPHI();
// Avoids attempting to dereference a sentintel which fails an assert
- if (MBBb == MBB.instr_end())
+ if (MBBb == MBB.end())
continue;
MachineInstr *MIb = &*MBBb;
@@ -4434,4 +4434,5 @@ void SelectionDAGISel::CannotYetSelect(SDNode *N) {
Msg << "unknown intrinsic #" << iid;
}
report_fatal_error(Twine(msg));
-}
\ No newline at end of file
+}
+
More information about the llvm-commits
mailing list