[llvm] [VPlan] Implement interleaving as VPlan-to-VPlan transform. (PR #95842)

[via llvm-commits]

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@@ -1049,6 +1061,11 @@ void VPlan::execute(VPTransformState *State) {
       // consistent placement of all induction updates.
       Instruction *Inc = cast<Instruction>(Phi->getIncomingValue(1));
       Inc->moveBefore(VectorLatchBB->getTerminator()->getPrevNode());
+
+      // When the VPlan has been unrolled, chain together the steps of the
+      // unrolled parts together.
+      if (isa<VPWidenIntOrFpInductionRecipe>(&R) && R.getNumOperands() == 4)
+        Inc->setOperand(0, State->get(R.getOperand(3), 0));
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ayalz wrote:

Of all header phi's, this is the only one to be backpatched here?

Have VPWidenIntOrFpInductionRecipe provide a getUnrolledPart() method which retrieves the last optional operand if exists, or null otherwise?

How would this look if/when all header-phi's are replaced by simple header-phi recipes prior to code-gen.

Independent nit: the above comment should also include rewiring (non-canonical) inductions
"  // Fix the latch value of canonical, reduction and first-order recurrences
  // phis in the vector loop."

https://github.com/llvm/llvm-project/pull/95842