[llvm] [AMDGPU][True16][MC] 16bit vsrc and vdst support in MC (PR #104510)

[Joe Nash via llvm-commits]

================
@@ -471,46 +471,46 @@ v_cvt_f16_u16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_
 v_cvt_f16_u16_e64_dpp v255, v255 clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: [0xff,0x80,0xd0,0xd5,0xfa,0x00,0x00,0x18,0xff,0x6f,0x05,0x30]
 
-v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[3,2,1,0]
+v_cvt_f32_f16_e64_dpp v5, v1.l quad_perm:[3,2,1,0]
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1b,0x00,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 quad_perm:[0,1,2,3]
+v_cvt_f32_f16_e64_dpp v5, v1.l quad_perm:[0,1,2,3]
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0xe4,0x00,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_mirror
+v_cvt_f32_f16_e64_dpp v5, v1.l row_mirror
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x40,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_half_mirror
+v_cvt_f32_f16_e64_dpp v5, v1.l row_half_mirror
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x41,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_shl:1
+v_cvt_f32_f16_e64_dpp v5, v1.l row_shl:1
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x01,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_shl:15
+v_cvt_f32_f16_e64_dpp v5, v1.l row_shl:15
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x0f,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_shr:1
+v_cvt_f32_f16_e64_dpp v5, v1.l row_shr:1
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x11,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_shr:15
+v_cvt_f32_f16_e64_dpp v5, v1.l row_shr:15
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x1f,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_ror:1
+v_cvt_f32_f16_e64_dpp v5, v1.l row_ror:1
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x21,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_ror:15
+v_cvt_f32_f16_e64_dpp v5, v1.l row_ror:15
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x2f,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 row_share:0 row_mask:0xf bank_mask:0xf
+v_cvt_f32_f16_e64_dpp v5, v1.l row_share:0 row_mask:0xf bank_mask:0xf
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x00,0x01,0x50,0x01,0xff]
 
-v_cvt_f32_f16_e64_dpp v5, v1 mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
+v_cvt_f32_f16_e64_dpp v5, v1.l mul:2 row_share:15 row_mask:0x0 bank_mask:0x1
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x08,0x01,0x5f,0x01,0x01]
 
-v_cvt_f32_f16_e64_dpp v5, v1 mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
+v_cvt_f32_f16_e64_dpp v5, v1.l mul:4 row_xmask:0 row_mask:0x1 bank_mask:0x3 bound_ctrl:1 fi:0
 // GFX11: [0x05,0x00,0x8b,0xd5,0xfa,0x00,0x00,0x10,0x01,0x60,0x09,0x13]
 
-v_cvt_f32_f16_e64_dpp v255, -|v255| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
+v_cvt_f32_f16_e64_dpp v255, -|v255.l| clamp div:2 row_xmask:15 row_mask:0x3 bank_mask:0x0 bound_ctrl:0 fi:1
 // GFX11: [0xff,0x81,0x8b,0xd5,0xfa,0x00,0x00,0x38,0xff,0x6f,0x05,0x30]
 
----------------
Sisyph wrote:

Looks like there should be tests of .h registers in this file?

https://github.com/llvm/llvm-project/pull/104510