[llvm] [AMDGPU][MC] Disallow null as saddr in flat instructions (PR #101730)

[Jun Wang via llvm-commits]

================
@@ -6205,6 +6205,12 @@ void SIInstrInfo::legalizeOperandsFLAT(MachineRegisterInfo &MRI,
     return;
 
   Register ToSGPR = readlaneVGPRToSGPR(SAddr->getReg(), MI, MRI);
+
+  const TargetRegisterClass *DeclaredRC =
+      getRegClass(MI.getDesc(), SAddr->getOperandNo(),
+                  MRI.getTargetRegisterInfo(), *MI.getParent()->getParent());
+
+  MRI.setRegClass(ToSGPR, DeclaredRC);
----------------
jwanggit86 wrote:

For the following mir code:
```
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64_xexec_xnull = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
      %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
```
In the SIFixSGPRCopies pass, `legalizeOperandsFLAT()` is called for the `GLOBAL_LOAD_DWORD_SADDR` instruction in the following call trace:
 ```
#0  llvm::SIRegisterInfo::getSGPRClassForBitWidth (BitWidth=64)
#1  0x0000555556ab1032 in llvm::SIRegisterInfo::getEquivalentSGPRClass (this=0x7ffff7e31380,
    VRC=0x55555f9eaaa0 <llvm::AMDGPU::VReg_64RegClass>)
#2  0x000055555697163b in llvm::SIInstrInfo::readlaneVGPRToSGPR (this=0x7ffff7e31330, SrcReg=..., UseMI=..., MRI=...)
#3  0x00005555569721c3 in llvm::SIInstrInfo::legalizeOperandsFLAT (this=0x7ffff7e31330, MRI=..., MI=...)
#4  0x0000555556974904 in llvm::SIInstrInfo::legalizeOperands (this=0x7ffff7e31330, MI=..., MDT=0x55555fc25558)
#5  0x0000555556978740 in llvm::SIInstrInfo::moveToVALUImpl (this=0x7ffff7e31330, Worklist=..., MDT=0x55555fc25558, Inst=...)
#6  0x0000555556976bbf in llvm::SIInstrInfo::moveToVALU (this=0x7ffff7e31330, Worklist=..., MDT=0x55555fc25558)
#7  0x0000555556901209 in (anonymous namespace)::SIFixSGPRCopies::lowerSpecialCase (this=0x55555fc24e80, MI=..., I=...)
```
Here in `readlaneVGPRToSGPR ()` it tries to get the SGPR equivalence of the src reg class, `VReg_64RegClass`. This leads to the call of `getSGPRClassForBitWidth()`, which, for 64b always returns `SReg_64RegClass`, which is not what we want here.
```cpp
const TargetRegisterClass *
SIRegisterInfo::getSGPRClassForBitWidth(unsigned BitWidth) {
  if (BitWidth == 16)
    return &AMDGPU::SGPR_LO16RegClass;
  if (BitWidth == 32)
    return &AMDGPU::SReg_32RegClass;
  if (BitWidth == 64)
    return &AMDGPU::SReg_64RegClass;
...
```
That's why in `legalizeOperandsFLAT()` we have to override it with the desired reg class for SAddr.

https://github.com/llvm/llvm-project/pull/101730