[llvm] [RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (PR #107138)

[Craig Topper via llvm-commits]

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@@ -39,6 +39,19 @@ def FCVT_S_BF16 : FPUnaryOp_r_frmlegacy<0b0100000, 0b00110, FPR32, FPR16, "fcvt.
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfbfmin] in {
+def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,
+                                   (bf16 FPR16:$truev), FPR16:$falsev),
+          (Select_FPR16_Using_CC_GPR GPR:$lhs, GPR:$rhs,
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topperc wrote:

This is using the same pseudo instruction as Zfhmin/Zfh since the register class is the same. That requires duplicating the isel patterns normally created by `SelectCC_GPR_rrirr`.

https://github.com/llvm/llvm-project/pull/107138