[llvm] [RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (PR #107138)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 3 11:23:04 PDT 2024
https://github.com/topperc created https://github.com/llvm/llvm-project/pull/107138
Select only needs branches and moves. We don't need to promote it. Promoting would canonicalize NaNs which select shouldn't do.
>From 94919758486e5070dcb945e1670e6bdc1fe0a97f Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Tue, 3 Sep 2024 11:19:51 -0700
Subject: [PATCH] [RISCV] Don't promove f16/bf16 SELECT with Zfhmin/Zfbfmin.
Select only needs branches and moves. We don't need to promote it.
Promoting would canonicalize NaNs which select shouldn't do.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 25 +-
.../lib/Target/RISCV/RISCVInstrInfoZfbfmin.td | 13 ++
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 8 +-
llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll | 102 ++++----
llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll | 102 +++-----
llvm/test/CodeGen/RISCV/half-select-fcmp.ll | 212 ++++++++---------
llvm/test/CodeGen/RISCV/half-select-icmp.ll | 218 +++++++-----------
7 files changed, 290 insertions(+), 390 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index f50d378ed97aa6..aba8d3edeb0764 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -434,19 +434,15 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
static const unsigned ZfhminZfbfminPromoteOps[] = {
- ISD::FMINNUM, ISD::FMAXNUM,
- ISD::FMAXIMUMNUM, ISD::FMINIMUMNUM,
- ISD::FADD, ISD::FSUB,
- ISD::FMUL, ISD::FMA,
- ISD::FDIV, ISD::FSQRT,
- ISD::STRICT_FMA, ISD::STRICT_FADD,
- ISD::STRICT_FSUB, ISD::STRICT_FMUL,
- ISD::STRICT_FDIV, ISD::STRICT_FSQRT,
- ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
- ISD::SETCC, ISD::FCEIL,
- ISD::FFLOOR, ISD::FTRUNC,
- ISD::FRINT, ISD::FROUND,
- ISD::FROUNDEVEN, ISD::SELECT};
+ ISD::FMINNUM, ISD::FMAXNUM, ISD::FMAXIMUMNUM,
+ ISD::FMINIMUMNUM, ISD::FADD, ISD::FSUB,
+ ISD::FMUL, ISD::FMA, ISD::FDIV,
+ ISD::FSQRT, ISD::STRICT_FMA, ISD::STRICT_FADD,
+ ISD::STRICT_FSUB, ISD::STRICT_FMUL, ISD::STRICT_FDIV,
+ ISD::STRICT_FSQRT, ISD::STRICT_FSETCC, ISD::STRICT_FSETCCS,
+ ISD::SETCC, ISD::FCEIL, ISD::FFLOOR,
+ ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
+ ISD::FROUNDEVEN};
if (Subtarget.hasStdExtZfbfmin()) {
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
@@ -454,6 +450,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FP_ROUND, MVT::bf16, Custom);
setOperationAction(ISD::ConstantFP, MVT::bf16, Expand);
setOperationAction(ISD::SELECT_CC, MVT::bf16, Expand);
+ setOperationAction(ISD::SELECT, MVT::bf16, Custom);
setOperationAction(ISD::BR_CC, MVT::bf16, Expand);
setOperationAction(ZfhminZfbfminPromoteOps, MVT::bf16, Promote);
setOperationAction(ISD::FREM, MVT::bf16, Promote);
@@ -467,7 +464,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
setOperationAction(FPRndMode, MVT::f16,
Subtarget.hasStdExtZfa() ? Legal : Custom);
- setOperationAction(ISD::SELECT, MVT::f16, Custom);
setOperationAction(ISD::IS_FPCLASS, MVT::f16, Custom);
} else {
setOperationAction(ZfhminZfbfminPromoteOps, MVT::f16, Promote);
@@ -484,6 +480,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
setCondCodeAction(FPCCToExpand, MVT::f16, Expand);
setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
+ setOperationAction(ISD::SELECT, MVT::f16, Custom);
setOperationAction(ISD::BR_CC, MVT::f16, Expand);
setOperationAction(ISD::FNEARBYINT, MVT::f16,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index 9028d31d08655b..cb26d55629f870 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -39,6 +39,19 @@ def FCVT_S_BF16 : FPUnaryOp_r_frmlegacy<0b0100000, 0b00110, FPR32, FPR16, "fcvt.
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtZfbfmin] in {
+def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), GPR:$rhs, cond,
+ (bf16 FPR16:$truev), FPR16:$falsev),
+ (Select_FPR16_Using_CC_GPR GPR:$lhs, GPR:$rhs,
+ (IntCCtoRISCVCC $cc), FPR16:$truev, FPR16:$falsev)>;
+
+// Explicitly select 0 in the condition to X0. The register coalescer doesn't
+// always do it.
+def : Pat<(riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), 0, cond,
+ (bf16 FPR16:$truev),
+ FPR16:$falsev),
+ (Select_FPR16_Using_CC_GPR GPR:$lhs, (XLenVT X0),
+ (IntCCtoRISCVCC $cc), FPR16:$truev, FPR16:$falsev)>;
+
/// Loads
def : LdPat<load, FLH, bf16>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index d60cf33567d6d0..760045be38edf4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -405,18 +405,16 @@ foreach Ext = ZfhExts in {
}
let Predicates = [HasStdExtZfh] in {
-defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16, f16>;
-
def PseudoFROUND_H : PseudoFROUND<FPR16, f16>;
} // Predicates = [HasStdExtZfh]
let Predicates = [HasStdExtZhinx] in {
-defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX, f16>;
-
def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX, f16>;
} // Predicates = [HasStdExtZhinx]
let Predicates = [HasStdExtZfhmin] in {
+defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16, f16>;
+
/// Loads
def : LdPat<load, FLH, f16>;
@@ -425,6 +423,8 @@ def : StPat<store, FSH, FPR16, f16>;
} // Predicates = [HasStdExtZfhmin]
let Predicates = [HasStdExtZhinxmin] in {
+defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX, f16>;
+
/// Loads
def : Pat<(f16 (load (AddrRegImm (XLenVT GPR:$rs1), simm12:$imm12))),
(COPY_TO_REGCLASS (LH GPR:$rs1, simm12:$imm12), GPRF16)>;
diff --git a/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll b/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
index 67acc9a772e357..2f7830c9c9d8ae 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-select-fcmp.ll
@@ -17,14 +17,13 @@ define bfloat @select_fcmp_false(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_oeq(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_oeq:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: feq.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a0, fa4, fa5
; CHECK-NEXT: bnez a0, .LBB1_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp oeq bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -39,9 +38,8 @@ define bfloat @select_fcmp_ogt(bfloat %a, bfloat %b) nounwind {
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: bnez a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ogt bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -56,9 +54,8 @@ define bfloat @select_fcmp_oge(bfloat %a, bfloat %b) nounwind {
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: bnez a0, .LBB3_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB3_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp oge bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -68,14 +65,13 @@ define bfloat @select_fcmp_oge(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_olt(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_olt:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: bnez a0, .LBB4_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp olt bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -85,14 +81,13 @@ define bfloat @select_fcmp_olt(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_ole(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_ole:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fle.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: bnez a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB5_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ole bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -102,16 +97,15 @@ define bfloat @select_fcmp_ole(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_one(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_one:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: flt.s a0, fa5, fa4
-; CHECK-NEXT: flt.s a1, fa4, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: flt.s a0, fa4, fa5
+; CHECK-NEXT: flt.s a1, fa5, fa4
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: bnez a0, .LBB6_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB6_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp one bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -123,14 +117,13 @@ define bfloat @select_fcmp_ord(bfloat %a, bfloat %b) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: feq.s a0, fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
-; CHECK-NEXT: feq.s a1, fa4, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: feq.s a1, fa5, fa5
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: bnez a0, .LBB7_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa4, fa5
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB7_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa4
; CHECK-NEXT: ret
%1 = fcmp ord bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -140,16 +133,15 @@ define bfloat @select_fcmp_ord(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_ueq(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_ueq:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: flt.s a0, fa5, fa4
-; CHECK-NEXT: flt.s a1, fa4, fa5
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: flt.s a0, fa4, fa5
+; CHECK-NEXT: flt.s a1, fa5, fa4
; CHECK-NEXT: or a0, a1, a0
; CHECK-NEXT: beqz a0, .LBB8_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB8_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ueq bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -159,14 +151,13 @@ define bfloat @select_fcmp_ueq(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_ugt(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_ugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fle.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: beqz a0, .LBB9_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB9_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ugt bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -176,14 +167,13 @@ define bfloat @select_fcmp_ugt(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_uge(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_uge:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: flt.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: beqz a0, .LBB10_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB10_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp uge bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -198,9 +188,8 @@ define bfloat @select_fcmp_ult(bfloat %a, bfloat %b) nounwind {
; CHECK-NEXT: fle.s a0, fa4, fa5
; CHECK-NEXT: beqz a0, .LBB11_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB11_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ult bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -215,9 +204,8 @@ define bfloat @select_fcmp_ule(bfloat %a, bfloat %b) nounwind {
; CHECK-NEXT: flt.s a0, fa4, fa5
; CHECK-NEXT: beqz a0, .LBB12_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB12_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp ule bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -227,14 +215,13 @@ define bfloat @select_fcmp_ule(bfloat %a, bfloat %b) nounwind {
define bfloat @select_fcmp_une(bfloat %a, bfloat %b) nounwind {
; CHECK-LABEL: select_fcmp_une:
; CHECK: # %bb.0:
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: feq.s a0, fa5, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
+; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
+; CHECK-NEXT: feq.s a0, fa4, fa5
; CHECK-NEXT: beqz a0, .LBB13_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa5, fa4
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB13_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = fcmp une bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
@@ -246,14 +233,13 @@ define bfloat @select_fcmp_uno(bfloat %a, bfloat %b) nounwind {
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: feq.s a0, fa5, fa5
-; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
-; CHECK-NEXT: feq.s a1, fa4, fa4
+; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK-NEXT: feq.s a1, fa5, fa5
; CHECK-NEXT: and a0, a1, a0
; CHECK-NEXT: beqz a0, .LBB14_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fmv.s fa4, fa5
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB14_2:
-; CHECK-NEXT: fcvt.bf16.s fa0, fa4
; CHECK-NEXT: ret
%1 = fcmp uno bfloat %a, %b
%2 = select i1 %1, bfloat %a, bfloat %b
diff --git a/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
index e802d53edfdedf..670218cacf0fe9 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-select-icmp.ll
@@ -1,20 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=riscv32 -mattr=+zfbfmin -verify-machineinstrs \
-; RUN: -target-abi ilp32f < %s | FileCheck %s
+; RUN: -target-abi ilp32f < %s | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: llc -mtriple=riscv64 -mattr=+zfbfmin -verify-machineinstrs \
-; RUN: -target-abi lp64f < %s | FileCheck %s
+; RUN: -target-abi lp64f < %s | FileCheck %s --check-prefixes=CHECK,RV64
define bfloat @select_icmp_eq(i32 signext %a, i32 signext %b, bfloat %c, bfloat %d) {
; CHECK-LABEL: select_icmp_eq:
; CHECK: # %bb.0:
; CHECK-NEXT: beq a0, a1, .LBB0_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB0_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -26,12 +22,8 @@ define bfloat @select_icmp_ne(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bne a0, a1, .LBB1_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB1_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -43,12 +35,8 @@ define bfloat @select_icmp_ugt(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a1, a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB2_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -60,12 +48,8 @@ define bfloat @select_icmp_uge(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a0, a1, .LBB3_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB3_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -77,12 +61,8 @@ define bfloat @select_icmp_ult(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bltu a0, a1, .LBB4_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB4_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -94,12 +74,8 @@ define bfloat @select_icmp_ule(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bgeu a1, a0, .LBB5_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB5_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -111,12 +87,8 @@ define bfloat @select_icmp_sgt(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: blt a1, a0, .LBB6_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB6_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -128,12 +100,8 @@ define bfloat @select_icmp_sge(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bge a0, a1, .LBB7_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB7_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -145,12 +113,8 @@ define bfloat @select_icmp_slt(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: blt a0, a1, .LBB8_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB8_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -162,12 +126,8 @@ define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat
; CHECK: # %bb.0:
; CHECK-NEXT: bge a1, a0, .LBB9_2
; CHECK-NEXT: # %bb.1:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; CHECK-NEXT: fmv.s fa0, fa1
; CHECK-NEXT: .LBB9_2:
-; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
; CHECK-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, bfloat %c, bfloat %d
@@ -175,24 +135,38 @@ define bfloat @select_icmp_sle(i32 signext %a, i32 signext %b, bfloat %c, bfloat
}
define bfloat @select_icmp_slt_one(i32 signext %a) {
-; CHECK-LABEL: select_icmp_slt_one:
-; CHECK: # %bb.0:
-; CHECK-NEXT: slti a0, a0, 1
-; CHECK-NEXT: fcvt.s.w fa5, a0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; RV32-LABEL: select_icmp_slt_one:
+; RV32: # %bb.0:
+; RV32-NEXT: slti a0, a0, 1
+; RV32-NEXT: fcvt.s.w fa5, a0
+; RV32-NEXT: fcvt.bf16.s fa0, fa5
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_icmp_slt_one:
+; RV64: # %bb.0:
+; RV64-NEXT: slti a0, a0, 1
+; RV64-NEXT: fcvt.s.l fa5, a0
+; RV64-NEXT: fcvt.bf16.s fa0, fa5
+; RV64-NEXT: ret
%1 = icmp slt i32 %a, 1
%2 = select i1 %1, bfloat 1.000000e+00, bfloat 0.000000e+00
ret bfloat %2
}
define bfloat @select_icmp_sgt_zero(i32 signext %a) {
-; CHECK-LABEL: select_icmp_sgt_zero:
-; CHECK: # %bb.0:
-; CHECK-NEXT: slti a0, a0, 1
-; CHECK-NEXT: fcvt.s.w fa5, a0
-; CHECK-NEXT: fcvt.bf16.s fa0, fa5
-; CHECK-NEXT: ret
+; RV32-LABEL: select_icmp_sgt_zero:
+; RV32: # %bb.0:
+; RV32-NEXT: slti a0, a0, 1
+; RV32-NEXT: fcvt.s.w fa5, a0
+; RV32-NEXT: fcvt.bf16.s fa0, fa5
+; RV32-NEXT: ret
+;
+; RV64-LABEL: select_icmp_sgt_zero:
+; RV64: # %bb.0:
+; RV64-NEXT: slti a0, a0, 1
+; RV64-NEXT: fcvt.s.l fa5, a0
+; RV64-NEXT: fcvt.bf16.s fa0, fa5
+; RV64-NEXT: ret
%1 = icmp sgt i32 %a, 0
%2 = select i1 %1, bfloat 0.000000e+00, bfloat 1.000000e+00
ret bfloat %2
diff --git a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
index 19bd36bcd690e7..b793c500fc397b 100644
--- a/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-fcmp.ll
@@ -62,26 +62,24 @@ define half @select_fcmp_oeq(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_oeq:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: bnez a0, .LBB1_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB1_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_oeq:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: feq.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: feq.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB1_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB1_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp oeq half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -114,21 +112,19 @@ define half @select_fcmp_ogt(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: bnez a0, .LBB2_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB2_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ogt:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: flt.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a1
+; CHECKIZHINXMIN-NEXT: flt.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB2_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB2_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ogt half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -161,21 +157,19 @@ define half @select_fcmp_oge(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: bnez a0, .LBB3_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB3_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_oge:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fle.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a1
+; CHECKIZHINXMIN-NEXT: fle.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB3_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB3_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp oge half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -203,26 +197,24 @@ define half @select_fcmp_olt(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_olt:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: bnez a0, .LBB4_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB4_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_olt:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: flt.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB4_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB4_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp olt half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -250,26 +242,24 @@ define half @select_fcmp_ole(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_ole:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: bnez a0, .LBB5_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB5_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ole:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fle.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: fle.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB5_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB5_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ole half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -301,30 +291,28 @@ define half @select_fcmp_one(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_one:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
+; CHECKIZFHMIN-NEXT: flt.s a1, fa5, fa4
; CHECKIZFHMIN-NEXT: or a0, a1, a0
; CHECKIZFHMIN-NEXT: bnez a0, .LBB6_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB6_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_one:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1
-; CHECKIZHINXMIN-NEXT: flt.s a3, a1, a0
-; CHECKIZHINXMIN-NEXT: or a2, a3, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: flt.s a4, a3, a2
+; CHECKIZHINXMIN-NEXT: flt.s a2, a2, a3
+; CHECKIZHINXMIN-NEXT: or a2, a2, a4
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB6_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB6_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp one half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -358,28 +346,26 @@ define half @select_fcmp_ord(half %a, half %b) nounwind {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa5
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT: feq.s a1, fa4, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECKIZFHMIN-NEXT: and a0, a1, a0
; CHECKIZFHMIN-NEXT: bnez a0, .LBB7_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa4, fa5
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB7_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa4
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ord:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: feq.s a2, a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: feq.s a3, a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: feq.s a2, a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: feq.s a3, a3, a3
; CHECKIZHINXMIN-NEXT: and a2, a3, a2
; CHECKIZHINXMIN-NEXT: bnez a2, .LBB7_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB7_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ord half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -411,30 +397,28 @@ define half @select_fcmp_ueq(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_ueq:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT: flt.s a1, fa4, fa5
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
+; CHECKIZFHMIN-NEXT: flt.s a1, fa5, fa4
; CHECKIZFHMIN-NEXT: or a0, a1, a0
; CHECKIZFHMIN-NEXT: beqz a0, .LBB8_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB8_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ueq:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1
-; CHECKIZHINXMIN-NEXT: flt.s a3, a1, a0
-; CHECKIZHINXMIN-NEXT: or a2, a3, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: flt.s a4, a3, a2
+; CHECKIZHINXMIN-NEXT: flt.s a2, a2, a3
+; CHECKIZHINXMIN-NEXT: or a2, a2, a4
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB8_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB8_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ueq half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -462,26 +446,24 @@ define half @select_fcmp_ugt(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_ugt:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fle.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: beqz a0, .LBB9_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB9_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ugt:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fle.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: fle.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB9_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB9_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ugt half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -509,26 +491,24 @@ define half @select_fcmp_uge(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_uge:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: flt.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: beqz a0, .LBB10_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB10_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_uge:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: flt.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB10_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB10_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp uge half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -561,21 +541,19 @@ define half @select_fcmp_ult(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fle.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: beqz a0, .LBB11_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB11_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ult:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fle.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a1
+; CHECKIZHINXMIN-NEXT: fle.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB11_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB11_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ult half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -608,21 +586,19 @@ define half @select_fcmp_ule(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: flt.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: beqz a0, .LBB12_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB12_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_ule:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: flt.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a1
+; CHECKIZHINXMIN-NEXT: flt.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB12_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB12_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp ule half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -650,26 +626,24 @@ define half @select_fcmp_une(half %a, half %b) nounwind {
;
; CHECKIZFHMIN-LABEL: select_fcmp_une:
; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
+; CHECKIZFHMIN-NEXT: feq.s a0, fa4, fa5
; CHECKIZFHMIN-NEXT: beqz a0, .LBB13_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa5, fa4
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB13_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_une:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: feq.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: feq.s a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB13_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB13_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp une half %a, %b
%2 = select i1 %1, half %a, half %b
@@ -703,28 +677,26 @@ define half @select_fcmp_uno(half %a, half %b) nounwind {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa5
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT: feq.s a1, fa4, fa4
+; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
+; CHECKIZFHMIN-NEXT: feq.s a1, fa5, fa5
; CHECKIZFHMIN-NEXT: and a0, a1, a0
; CHECKIZFHMIN-NEXT: beqz a0, .LBB14_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fmv.s fa4, fa5
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB14_2:
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa4
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_fcmp_uno:
; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
-; CHECKIZHINXMIN-NEXT: feq.s a2, a1, a1
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECKIZHINXMIN-NEXT: feq.s a3, a0, a0
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a1
+; CHECKIZHINXMIN-NEXT: feq.s a2, a2, a2
+; CHECKIZHINXMIN-NEXT: fcvt.s.h a3, a0
+; CHECKIZHINXMIN-NEXT: feq.s a3, a3, a3
; CHECKIZHINXMIN-NEXT: and a2, a3, a2
; CHECKIZHINXMIN-NEXT: beqz a2, .LBB14_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
; CHECKIZHINXMIN-NEXT: mv a0, a1
; CHECKIZHINXMIN-NEXT: .LBB14_2:
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
; CHECKIZHINXMIN-NEXT: ret
%1 = fcmp uno half %a, %b
%2 = select i1 %1, half %a, half %b
diff --git a/llvm/test/CodeGen/RISCV/half-select-icmp.ll b/llvm/test/CodeGen/RISCV/half-select-icmp.ll
index 0e4030049e919c..51f465743f8809 100644
--- a/llvm/test/CodeGen/RISCV/half-select-icmp.ll
+++ b/llvm/test/CodeGen/RISCV/half-select-icmp.ll
@@ -8,13 +8,13 @@
; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
; RUN: -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
-; RUN: -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZFHINXMIN %s
; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
-; RUN: -target-abi=lp64 | FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECK-LABEL: select_icmp_eq:
@@ -38,24 +38,17 @@ define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: beq a0, a1, .LBB0_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB0_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_eq:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: beq a0, a1, .LBB0_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB0_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp eq i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -84,24 +77,17 @@ define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bne a0, a1, .LBB1_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB1_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_ne:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bne a0, a1, .LBB1_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB1_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ne i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -130,24 +116,17 @@ define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bltu a1, a0, .LBB2_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB2_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_ugt:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bltu a1, a0, .LBB2_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB2_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ugt i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -176,24 +155,17 @@ define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bgeu a0, a1, .LBB3_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB3_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_uge:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bgeu a0, a1, .LBB3_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB3_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp uge i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -222,24 +194,17 @@ define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bltu a0, a1, .LBB4_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB4_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_ult:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bltu a0, a1, .LBB4_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB4_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -268,24 +233,17 @@ define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bgeu a1, a0, .LBB5_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB5_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_ule:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bgeu a1, a0, .LBB5_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB5_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp ule i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -314,24 +272,17 @@ define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: blt a1, a0, .LBB6_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB6_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_sgt:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: blt a1, a0, .LBB6_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB6_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sgt i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -360,24 +311,17 @@ define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bge a0, a1, .LBB7_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB7_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_sge:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bge a0, a1, .LBB7_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB7_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sge i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -406,24 +350,17 @@ define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: blt a0, a1, .LBB8_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB8_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_slt:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: blt a0, a1, .LBB8_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB8_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -452,24 +389,17 @@ define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: bge a1, a0, .LBB9_2
; CHECKIZFHMIN-NEXT: # %bb.1:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
+; CHECKIZFHMIN-NEXT: fmv.s fa0, fa1
; CHECKIZFHMIN-NEXT: .LBB9_2:
-; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
; CHECKIZHINXMIN-LABEL: select_icmp_sle:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: bge a1, a0, .LBB9_2
; CHECKIZHINXMIN-NEXT: # %bb.1:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a3
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; CHECKIZHINXMIN-NEXT: mv a2, a3
; CHECKIZHINXMIN-NEXT: .LBB9_2:
-; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a2
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT: mv a0, a2
; CHECKIZHINXMIN-NEXT: ret
%1 = icmp sle i32 %a, %b
%2 = select i1 %1, half %c, half %d
@@ -489,19 +419,33 @@ define half @select_icmp_slt_one(i32 signext %a) {
; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
; CHECKIZHINX-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: select_icmp_slt_one:
-; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: slti a0, a0, 1
-; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
-;
-; CHECKIZHINXMIN-LABEL: select_icmp_slt_one:
-; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
-; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: select_icmp_slt_one:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: slti a0, a0, 1
+; RV32IZFHMIN-NEXT: fcvt.s.w fa5, a0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: select_icmp_slt_one:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: slti a0, a0, 1
+; RV64IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZFHINXMIN-LABEL: select_icmp_slt_one:
+; RV32IZFHINXMIN: # %bb.0:
+; RV32IZFHINXMIN-NEXT: slti a0, a0, 1
+; RV32IZFHINXMIN-NEXT: fcvt.s.w a0, a0
+; RV32IZFHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZFHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: select_icmp_slt_one:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: slti a0, a0, 1
+; RV64IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: ret
%1 = icmp slt i32 %a, 1
%2 = select i1 %1, half 1.000000e+00, half 0.000000e+00
ret half %2
@@ -520,19 +464,33 @@ define half @select_icmp_sgt_zero(i32 signext %a) {
; CHECKIZHINX-NEXT: fcvt.h.w a0, a0
; CHECKIZHINX-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: select_icmp_sgt_zero:
-; CHECKIZFHMIN: # %bb.0:
-; CHECKIZFHMIN-NEXT: slti a0, a0, 1
-; CHECKIZFHMIN-NEXT: fcvt.s.w fa5, a0
-; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT: ret
-;
-; CHECKIZHINXMIN-LABEL: select_icmp_sgt_zero:
-; CHECKIZHINXMIN: # %bb.0:
-; CHECKIZHINXMIN-NEXT: slti a0, a0, 1
-; CHECKIZHINXMIN-NEXT: fcvt.s.w a0, a0
-; CHECKIZHINXMIN-NEXT: fcvt.h.s a0, a0
-; CHECKIZHINXMIN-NEXT: ret
+; RV32IZFHMIN-LABEL: select_icmp_sgt_zero:
+; RV32IZFHMIN: # %bb.0:
+; RV32IZFHMIN-NEXT: slti a0, a0, 1
+; RV32IZFHMIN-NEXT: fcvt.s.w fa5, a0
+; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV32IZFHMIN-NEXT: ret
+;
+; RV64IZFHMIN-LABEL: select_icmp_sgt_zero:
+; RV64IZFHMIN: # %bb.0:
+; RV64IZFHMIN-NEXT: slti a0, a0, 1
+; RV64IZFHMIN-NEXT: fcvt.s.l fa5, a0
+; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
+; RV64IZFHMIN-NEXT: ret
+;
+; RV32IZFHINXMIN-LABEL: select_icmp_sgt_zero:
+; RV32IZFHINXMIN: # %bb.0:
+; RV32IZFHINXMIN-NEXT: slti a0, a0, 1
+; RV32IZFHINXMIN-NEXT: fcvt.s.w a0, a0
+; RV32IZFHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV32IZFHINXMIN-NEXT: ret
+;
+; RV64IZHINXMIN-LABEL: select_icmp_sgt_zero:
+; RV64IZHINXMIN: # %bb.0:
+; RV64IZHINXMIN-NEXT: slti a0, a0, 1
+; RV64IZHINXMIN-NEXT: fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT: fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT: ret
%1 = icmp sgt i32 %a, 0
%2 = select i1 %1, half 0.000000e+00, half 1.000000e+00
ret half %2
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