[llvm] [SLP]Initial support for non-power-of-2 (but still whole register) number of elements in operands. (PR #106449)

[Philip Reames via llvm-commits]

preames wrote:

> Looks like it requires to use a new TTI entry instead of this one, since it does not work as expected for RISCV. I will add it.

Unless I'm missing something, simple querying the cost of the <6 x i64> type via the existing interfaces should give correct costs on RISCV.  I don't know if the work for that has been done for other targets, but I do not see a need for a new TTI call here.

https://github.com/llvm/llvm-project/pull/106449