[llvm] [RISCV] Rename sf_vcix_state to sf.vcix_state (PR #107115)

[Brandon Wu via llvm-commits]

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/107115

This PR: https://github.com/llvm/llvm-project/pull/106995 names the
vendor CSR in a wrong way, it should be `sf.` rather than `sf_` for
prefix.


>From 1c432c5cf627d15a28f96e3ee4b342575b45fd2d Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Tue, 3 Sep 2024 06:56:38 -0700
Subject: [PATCH] [RISCV] Rename sf_vcix_state to sf.vcix_state

This PR: https://github.com/llvm/llvm-project/pull/106995 names the
vendor CSR in a wrong way, it should be `sf.` rather than `sf_` for
prefix.
---
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index ce9f9e39154c2b..5725d8eda88ced 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -665,4 +665,4 @@ def FRM    : RISCVReg<0, "frm">;
 def SSP    : RISCVReg<0, "ssp">;
 
 // Dummy SiFive VCIX state register
-def SF_VCIX_STATE : RISCVReg<0, "sf_vcix_state">;
+def SF_VCIX_STATE : RISCVReg<0, "sf.vcix_state">;