[llvm] f77f604 - [CodeGen] Remove checks that implicit operands are implicit

Jay Foad via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 3 05:09:23 PDT 2024


Author: Jay Foad
Date: 2024-09-03T13:09:17+01:00
New Revision: f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d

URL: https://github.com/llvm/llvm-project/commit/f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d
DIFF: https://github.com/llvm/llvm-project/commit/f77f60400f7a4c0c50bc3e3144cdade3bdf9aa3d.diff

LOG: [CodeGen] Remove checks that implicit operands are implicit

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/MachineInstr.h
    llvm/lib/CodeGen/MachineInstr.cpp
    llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 62667cc8ef3800..239387a81ab581 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -642,7 +642,7 @@ class MachineInstr
   /// Returns true if the instruction has implicit definition.
   bool hasImplicitDef() const {
     for (const MachineOperand &MO : implicit_operands())
-      if (MO.isDef() && MO.isImplicit())
+      if (MO.isDef())
         return true;
     return false;
   }

diff  --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index f21910ee3a444a..a0f4040828383e 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1041,8 +1041,8 @@ unsigned MachineInstr::getBundleSize() const {
 /// Returns true if the MachineInstr has an implicit-use operand of exactly
 /// the given register (not considering sub/super-registers).
 bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const {
-  for (const MachineOperand &MO : operands()) {
-    if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
+  for (const MachineOperand &MO : implicit_operands()) {
+    if (MO.isReg() && MO.isUse() && MO.getReg() == Reg)
       return true;
   }
   return false;

diff  --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index 25dfacca956bb8..42440bc36f2498 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -1578,7 +1578,7 @@ void ARMExpandPseudo::CMSESaveClearFPRegsV81(MachineBasicBlock &MBB,
                         // the encoding.
     // Mark non-live registers as undef
     for (MachineOperand &MO : VLSTM->implicit_operands()) {
-      if (MO.isReg() && MO.isImplicit() && !MO.isDef()) {
+      if (MO.isReg() && !MO.isDef()) {
         Register Reg = MO.getReg();
         MO.setIsUndef(!LiveRegs.contains(Reg));
       }


        


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