[llvm] fe1a1ee - [Tests] Regenerate test checks (NFC)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 3 02:42:58 PDT 2024
Author: Nikita Popov
Date: 2024-09-03T11:42:47+02:00
New Revision: fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
URL: https://github.com/llvm/llvm-project/commit/fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c
DIFF: https://github.com/llvm/llvm-project/commit/fe1a1eee2ff864d2ba00ad67e6360b7178e67d5c.diff
LOG: [Tests] Regenerate test checks (NFC)
Added:
Modified:
llvm/test/Transforms/JumpThreading/pr22086.ll
llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
llvm/test/Transforms/SCCP/loadtest2.ll
llvm/test/Transforms/SCCP/select.ll
Removed:
################################################################################
diff --git a/llvm/test/Transforms/JumpThreading/pr22086.ll b/llvm/test/Transforms/JumpThreading/pr22086.ll
index 38a4fe470f1e38..c7f9fcdbd34627 100644
--- a/llvm/test/Transforms/JumpThreading/pr22086.ll
+++ b/llvm/test/Transforms/JumpThreading/pr22086.ll
@@ -1,13 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -passes=jump-threading < %s | FileCheck %s
-; CHECK-LABEL: @f(
-; CHECK-LABEL: entry:
-; CHECK-NEXT: br label %[[loop:.*]]
-; CHECK: [[loop]]:
-; CHECK-NEXT: br label %[[loop]]
define void @f() {
+; CHECK-LABEL: define void @f() {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: br label %[[LOR_RHS:.*]]
+; CHECK: [[LOR_RHS]]:
+; CHECK-NEXT: br label %[[LOR_RHS]]
+;
entry:
br label %for.cond1
diff --git a/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll b/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
index 8874373f4e4952..274a84dc4c112d 100644
--- a/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
+++ b/llvm/test/Transforms/LoopUnroll/unroll-cleanup.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; PR23524
; The test is to check redundency produced by loop unroll pass
; should be cleaned up by later pass.
@@ -10,8 +11,6 @@
; should be merged to:
; %dec18.1 = add nsw i32 %dec18.in, -2
;
-; CHECK-LABEL: @_Z3fn1v(
-; CHECK: %dec18.1 = add nsw i32 %dec18.in, -2
; ModuleID = '<stdin>'
target triple = "x86_64-unknown-linux-gnu"
@@ -21,9 +20,99 @@ target triple = "x86_64-unknown-linux-gnu"
; Function Attrs: nounwind uwtable
define void @_Z3fn1v() #0 {
+; CHECK-LABEL: define void @_Z3fn1v(
+; CHECK-SAME: ) local_unnamed_addr #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[ENTRY:.*]]:
+; CHECK-NEXT: [[TMP:%.*]] = load i32, ptr @b, align 4
+; CHECK-NEXT: [[TOBOOL20:%.*]] = icmp eq i32 [[TMP]], 0
+; CHECK-NEXT: br i1 [[TOBOOL20]], label %[[FOR_END6:.*]], label %[[FOR_BODY:.*]]
+; CHECK: [[FOR_COND_LOOPEXIT_LOOPEXIT:.*]]:
+; CHECK-NEXT: [[ADD_PTR_LCSSA:%.*]] = phi ptr [ [[ADD_PTR_LCSSA_UNR:%.*]], %[[FOR_BODY3_PROL_LOOPEXIT:.*]] ], [ [[ADD_PTR_1:%.*]], %[[FOR_INC_1:.*]] ]
+; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[A_021:%.*]], i64 1
+; CHECK-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP1:%.*]]
+; CHECK-NEXT: [[TMP1_PRE:%.*]] = load i32, ptr @b, align 4
+; CHECK-NEXT: br label %[[FOR_COND_LOOPEXIT:.*]]
+; CHECK: [[FOR_COND_LOOPEXIT]]:
+; CHECK-NEXT: [[T1:%.*]] = phi i32 [ [[T12:%.*]], %[[FOR_BODY]] ], [ [[TMP1_PRE]], %[[FOR_COND_LOOPEXIT_LOOPEXIT]] ]
+; CHECK-NEXT: [[R_1_LCSSA:%.*]] = phi ptr [ [[R_022:%.*]], %[[FOR_BODY]] ], [ [[ADD_PTR_LCSSA]], %[[FOR_COND_LOOPEXIT_LOOPEXIT]] ]
+; CHECK-NEXT: [[A_1_LCSSA:%.*]] = phi ptr [ [[A_021]], %[[FOR_BODY]] ], [ [[SCEVGEP1]], %[[FOR_COND_LOOPEXIT_LOOPEXIT]] ]
+; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[T1]], 0
+; CHECK-NEXT: br i1 [[TOBOOL]], label %[[FOR_END6]], label %[[FOR_BODY]]
+; CHECK: [[FOR_BODY]]:
+; CHECK-NEXT: [[T12]] = phi i32 [ [[T1]], %[[FOR_COND_LOOPEXIT]] ], [ [[TMP]], %[[ENTRY]] ]
+; CHECK-NEXT: [[R_022]] = phi ptr [ [[R_1_LCSSA]], %[[FOR_COND_LOOPEXIT]] ], [ undef, %[[ENTRY]] ]
+; CHECK-NEXT: [[A_021]] = phi ptr [ [[A_1_LCSSA]], %[[FOR_COND_LOOPEXIT]] ], [ undef, %[[ENTRY]] ]
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @c, align 4
+; CHECK-NEXT: [[TOBOOL215:%.*]] = icmp eq i32 [[TMP2]], 0
+; CHECK-NEXT: br i1 [[TOBOOL215]], label %[[FOR_COND_LOOPEXIT]], label %[[FOR_BODY3_PREHEADER:.*]]
+; CHECK: [[FOR_BODY3_PREHEADER]]:
+; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[TMP2]], -1
+; CHECK-NEXT: [[TMP1]] = zext i32 [[TMP0]] to i64
+; CHECK-NEXT: [[XTRAITER:%.*]] = and i32 [[TMP2]], 1
+; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i32 [[XTRAITER]], 0
+; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label %[[FOR_BODY3_PROL_LOOPEXIT]], label %[[FOR_BODY3_PROL:.*]]
+; CHECK: [[FOR_BODY3_PROL]]:
+; CHECK-NEXT: [[DEC18_PROL:%.*]] = add nsw i32 [[TMP2]], -1
+; CHECK-NEXT: [[TMP3_PROL:%.*]] = load i8, ptr [[A_021]], align 1
+; CHECK-NEXT: [[CMP_PROL:%.*]] = icmp eq i8 [[TMP3_PROL]], 0
+; CHECK-NEXT: br i1 [[CMP_PROL]], label %[[IF_THEN_PROL:.*]], label %[[FOR_INC_PROL:.*]]
+; CHECK: [[IF_THEN_PROL]]:
+; CHECK-NEXT: [[ARRAYIDX_PROL:%.*]] = getelementptr inbounds i8, ptr [[R_022]], i64 2
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX_PROL]], align 2
+; CHECK-NEXT: store i16 0, ptr [[R_022]], align 2
+; CHECK-NEXT: [[ARRAYIDX5_PROL:%.*]] = getelementptr inbounds i8, ptr [[R_022]], i64 4
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX5_PROL]], align 2
+; CHECK-NEXT: br label %[[FOR_INC_PROL]]
+; CHECK: [[FOR_INC_PROL]]:
+; CHECK-NEXT: [[INCDEC_PTR_PROL:%.*]] = getelementptr inbounds i8, ptr [[A_021]], i64 1
+; CHECK-NEXT: [[ADD_PTR_PROL:%.*]] = getelementptr inbounds i8, ptr [[R_022]], i64 6
+; CHECK-NEXT: br label %[[FOR_BODY3_PROL_LOOPEXIT]]
+; CHECK: [[FOR_BODY3_PROL_LOOPEXIT]]:
+; CHECK-NEXT: [[ADD_PTR_LCSSA_UNR]] = phi ptr [ poison, %[[FOR_BODY3_PREHEADER]] ], [ [[ADD_PTR_PROL]], %[[FOR_INC_PROL]] ]
+; CHECK-NEXT: [[DEC18_IN_UNR:%.*]] = phi i32 [ [[TMP2]], %[[FOR_BODY3_PREHEADER]] ], [ [[DEC18_PROL]], %[[FOR_INC_PROL]] ]
+; CHECK-NEXT: [[R_117_UNR:%.*]] = phi ptr [ [[R_022]], %[[FOR_BODY3_PREHEADER]] ], [ [[ADD_PTR_PROL]], %[[FOR_INC_PROL]] ]
+; CHECK-NEXT: [[A_116_UNR:%.*]] = phi ptr [ [[A_021]], %[[FOR_BODY3_PREHEADER]] ], [ [[INCDEC_PTR_PROL]], %[[FOR_INC_PROL]] ]
+; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i32 [[TMP0]], 0
+; CHECK-NEXT: br i1 [[TMP4]], label %[[FOR_COND_LOOPEXIT_LOOPEXIT]], label %[[FOR_BODY3:.*]]
+; CHECK: [[FOR_BODY3]]:
+; CHECK-NEXT: [[DEC18_IN:%.*]] = phi i32 [ [[DEC18_1:%.*]], %[[FOR_INC_1]] ], [ [[DEC18_IN_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
+; CHECK-NEXT: [[R_117:%.*]] = phi ptr [ [[ADD_PTR_1]], %[[FOR_INC_1]] ], [ [[R_117_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
+; CHECK-NEXT: [[A_116:%.*]] = phi ptr [ [[INCDEC_PTR_1:%.*]], %[[FOR_INC_1]] ], [ [[A_116_UNR]], %[[FOR_BODY3_PROL_LOOPEXIT]] ]
+; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr [[A_116]], align 1
+; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[TMP3]], 0
+; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[FOR_INC:.*]]
+; CHECK: [[IF_THEN]]:
+; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i8, ptr [[R_117]], i64 2
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX]], align 2
+; CHECK-NEXT: store i16 0, ptr [[R_117]], align 2
+; CHECK-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i8, ptr [[R_117]], i64 4
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX5]], align 2
+; CHECK-NEXT: br label %[[FOR_INC]]
+; CHECK: [[FOR_INC]]:
+; CHECK-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i8, ptr [[A_116]], i64 1
+; CHECK-NEXT: [[DEC18_1]] = add nsw i32 [[DEC18_IN]], -2
+; CHECK-NEXT: [[TMP3_1:%.*]] = load i8, ptr [[INCDEC_PTR]], align 1
+; CHECK-NEXT: [[CMP_1:%.*]] = icmp eq i8 [[TMP3_1]], 0
+; CHECK-NEXT: br i1 [[CMP_1]], label %[[IF_THEN_1:.*]], label %[[FOR_INC_1]]
+; CHECK: [[IF_THEN_1]]:
+; CHECK-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i8, ptr [[R_117]], i64 6
+; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds i8, ptr [[R_117]], i64 8
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX_1]], align 2
+; CHECK-NEXT: store i16 0, ptr [[ADD_PTR]], align 2
+; CHECK-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr inbounds i8, ptr [[R_117]], i64 10
+; CHECK-NEXT: store i16 0, ptr [[ARRAYIDX5_1]], align 2
+; CHECK-NEXT: br label %[[FOR_INC_1]]
+; CHECK: [[FOR_INC_1]]:
+; CHECK-NEXT: [[INCDEC_PTR_1]] = getelementptr inbounds i8, ptr [[A_116]], i64 2
+; CHECK-NEXT: [[ADD_PTR_1]] = getelementptr inbounds i8, ptr [[R_117]], i64 12
+; CHECK-NEXT: [[TOBOOL2_1:%.*]] = icmp eq i32 [[DEC18_1]], 0
+; CHECK-NEXT: br i1 [[TOBOOL2_1]], label %[[FOR_COND_LOOPEXIT_LOOPEXIT]], label %[[FOR_BODY3]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[FOR_END6]]:
+; CHECK-NEXT: ret void
+;
entry:
- %tmp = load i32, ptr @b, align 4
- %tobool20 = icmp eq i32 %tmp, 0
+ %t = load i32, ptr @b, align 4
+ %tobool20 = icmp eq i32 %t, 0
br i1 %tobool20, label %for.end6, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry
@@ -37,27 +126,27 @@ for.cond1.for.cond.loopexit_crit_edge: ; preds = %for.inc
for.cond.loopexit: ; preds = %for.body, %for.cond1.for.cond.loopexit_crit_edge
%r.1.lcssa = phi ptr [ %add.ptr.lcssa, %for.cond1.for.cond.loopexit_crit_edge ], [ %r.022, %for.body ]
%a.1.lcssa = phi ptr [ %incdec.ptr.lcssa, %for.cond1.for.cond.loopexit_crit_edge ], [ %a.021, %for.body ]
- %tmp1 = load i32, ptr @b, align 4
- %tobool = icmp eq i32 %tmp1, 0
+ %t1 = load i32, ptr @b, align 4
+ %tobool = icmp eq i32 %t1, 0
br i1 %tobool, label %for.cond.for.end6_crit_edge, label %for.body
for.body: ; preds = %for.cond.loopexit, %for.body.lr.ph
%r.022 = phi ptr [ undef, %for.body.lr.ph ], [ %r.1.lcssa, %for.cond.loopexit ]
%a.021 = phi ptr [ undef, %for.body.lr.ph ], [ %a.1.lcssa, %for.cond.loopexit ]
- %tmp2 = load i32, ptr @c, align 4
- %tobool215 = icmp eq i32 %tmp2, 0
+ %t2 = load i32, ptr @c, align 4
+ %tobool215 = icmp eq i32 %t2, 0
br i1 %tobool215, label %for.cond.loopexit, label %for.body3.lr.ph
for.body3.lr.ph: ; preds = %for.body
br label %for.body3
for.body3: ; preds = %for.inc, %for.body3.lr.ph
- %dec18.in = phi i32 [ %tmp2, %for.body3.lr.ph ], [ %dec18, %for.inc ]
+ %dec18.in = phi i32 [ %t2, %for.body3.lr.ph ], [ %dec18, %for.inc ]
%r.117 = phi ptr [ %r.022, %for.body3.lr.ph ], [ %add.ptr, %for.inc ]
%a.116 = phi ptr [ %a.021, %for.body3.lr.ph ], [ %incdec.ptr, %for.inc ]
%dec18 = add nsw i32 %dec18.in, -1
- %tmp3 = load i8, ptr %a.116, align 1
- %cmp = icmp eq i8 %tmp3, 0
+ %t3 = load i8, ptr %a.116, align 1
+ %cmp = icmp eq i8 %t3, 0
br i1 %cmp, label %if.then, label %for.inc
if.then: ; preds = %for.body3
@@ -83,3 +172,7 @@ for.end6: ; preds = %for.cond.for.end6_c
!0 = !{!0, !1}
!1 = !{!"llvm.loop.unroll.count", i32 2}
+;.
+; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]]}
+; CHECK: [[META1]] = !{!"llvm.loop.unroll.disable"}
+;.
diff --git a/llvm/test/Transforms/SCCP/loadtest2.ll b/llvm/test/Transforms/SCCP/loadtest2.ll
index 439764837835bc..28cea91d056e43 100644
--- a/llvm/test/Transforms/SCCP/loadtest2.ll
+++ b/llvm/test/Transforms/SCCP/loadtest2.ll
@@ -1,12 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -data-layout="E-p:32:32" -passes=ipsccp -S | FileCheck %s
@j = internal global i32 undef, align 4
; Make sure we do not mark loads from undef as overdefined.
define i32 @test5(i32 %b) {
-; CHECK-LABEL: define i32 @test5(i32 %b)
-; CHECK-NEXT: %add = add nsw i32 undef, %b
-; CHECK-NEXT: ret i32 %add
+; CHECK-LABEL: define i32 @test5(
+; CHECK-SAME: i32 [[B:%.*]]) {
+; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 undef, [[B]]
+; CHECK-NEXT: ret i32 [[ADD]]
;
%l = load i32, ptr @j, align 4
%add = add nsw i32 %l, %b
diff --git a/llvm/test/Transforms/SCCP/select.ll b/llvm/test/Transforms/SCCP/select.ll
index fac37402990660..dfe44bb108f54c 100644
--- a/llvm/test/Transforms/SCCP/select.ll
+++ b/llvm/test/Transforms/SCCP/select.ll
@@ -1,32 +1,36 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=sccp -S | FileCheck %s
define i32 @test1(i1 %C) {
; CHECK-LABEL: define i32 @test1(
-; CHECK-NEXT: ret i32 0
+; CHECK-SAME: i1 [[C:%.*]]) {
+; CHECK-NEXT: ret i32 0
;
- %X = select i1 %C, i32 0, i32 0 ; <i32> [#uses=1]
- ret i32 %X
+ %X = select i1 %C, i32 0, i32 0
+ ret i32 %X
}
define i32 @test2(i1 %C) {
; CHECK-LABEL: define i32 @test2(
-; CHECK-NEXT: ret i32 0
+; CHECK-SAME: i1 [[C:%.*]]) {
+; CHECK-NEXT: ret i32 0
;
- %X = select i1 %C, i32 0, i32 undef ; <i32> [#uses=1]
- ret i32 %X
+ %X = select i1 %C, i32 0, i32 undef
+ ret i32 %X
}
define i1 @f2(i32 %x, i1 %cmp) {
-; CHECK-LABEL: define i1 @f2(i32 %x, i1 %cmp) {
-; CHECK-NEXT: %sel.1 = select i1 %cmp, i32 %x, i32 10
-; CHECK-NEXT: %c.1 = icmp sgt i32 %sel.1, 300
-; CHECK-NEXT: %c.2 = icmp sgt i32 %sel.1, 100
-; CHECK-NEXT: %c.3 = icmp eq i32 %sel.1, 50
-; CHECK-NEXT: %c.4 = icmp slt i32 %sel.1, 9
-; CHECK-NEXT: %res.1 = add i1 %c.1, %c.2
-; CHECK-NEXT: %res.2 = add i1 %res.1, %c.3
-; CHECK-NEXT: %res.3 = add i1 %res.2, %c.4
-; CHECK-NEXT: ret i1 %res.3
+; CHECK-LABEL: define i1 @f2(
+; CHECK-SAME: i32 [[X:%.*]], i1 [[CMP:%.*]]) {
+; CHECK-NEXT: [[SEL_1:%.*]] = select i1 [[CMP]], i32 [[X]], i32 10
+; CHECK-NEXT: [[C_1:%.*]] = icmp sgt i32 [[SEL_1]], 300
+; CHECK-NEXT: [[C_2:%.*]] = icmp sgt i32 [[SEL_1]], 100
+; CHECK-NEXT: [[C_3:%.*]] = icmp eq i32 [[SEL_1]], 50
+; CHECK-NEXT: [[C_4:%.*]] = icmp slt i32 [[SEL_1]], 9
+; CHECK-NEXT: [[RES_1:%.*]] = add i1 [[C_1]], [[C_2]]
+; CHECK-NEXT: [[RES_2:%.*]] = add i1 [[RES_1]], [[C_3]]
+; CHECK-NEXT: [[RES_3:%.*]] = add i1 [[RES_2]], [[C_4]]
+; CHECK-NEXT: ret i1 [[RES_3]]
;
%sel.1 = select i1 %cmp, i32 %x, i32 10
%c.1 = icmp sgt i32 %sel.1, 300
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