[llvm] [AArch64][SLP] Add NFC test cases for floating point reductions (PR #106507)

[Sushant Gokhale via llvm-commits]

sushgokh wrote:

> Sure I can try that. If you put a patch for it I can give it a test in a few places.

```
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4056,6 +4059,23 @@ AArch64TTIImpl::getArithmeticReductionCost(unsigned Opcode, VectorType *ValTy,
   switch (ISD) {
   default:
     break;
+  case ISD::FADD: {
+    if (MTy.isVector()) {
+      unsigned NumElts = MTy.getVectorNumElements();
+      if (ValTy->getElementCount().getFixedValue() >= 2 && NumElts >= 2 &&
+          isPowerOf2_32(NumElts)
+          //&& ST->getProcFamily() == AArch64Subtarget::NeoverseV2)
+      ) {
+        // Floating point reductions are lowered to series of faddp
+        // instructions.
+        // For Neoverse-V1 onwards, for `faddp` instruction, Latency=2 and
+        // Throughput=4.
+        unsigned NumFAddpIns = Log2_32(NumElts);
+        return (LT.first - 1) +
+               /*Latency=*/2 * divideCeil(NumFAddpIns, /*Throughput=*/4);
+      }
+    }
+  } break;
   case ISD::ADD:
     if (const auto *Entry = CostTableLookup(CostTblNoPairwise, ISD, MTy))
       return (LT.first - 1) + Entry->Cost;
```

https://github.com/llvm/llvm-project/pull/106507