[llvm] dc19b59 - [RISCV] Rename test cases in bfloat-arith.ll and half-arith.ll. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 2 19:02:19 PDT 2024
Author: Craig Topper
Date: 2024-09-02T19:00:38-07:00
New Revision: dc19b59ea2502193c0e7bc16bb7d711c8053edcf
URL: https://github.com/llvm/llvm-project/commit/dc19b59ea2502193c0e7bc16bb7d711c8053edcf
DIFF: https://github.com/llvm/llvm-project/commit/dc19b59ea2502193c0e7bc16bb7d711c8053edcf.diff
LOG: [RISCV] Rename test cases in bfloat-arith.ll and half-arith.ll. NFC
Use _bf16 or _h instead of _s. The _s was copied from float-arith.ll
Added:
Modified:
llvm/test/CodeGen/RISCV/bfloat-arith.ll
llvm/test/CodeGen/RISCV/half-arith.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/RISCV/bfloat-arith.ll b/llvm/test/CodeGen/RISCV/bfloat-arith.ll
index 20150b5994b78d..965d7e0132e60b 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-arith.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-arith.ll
@@ -7,8 +7,8 @@
; These tests descend from float-arith.ll, where each function was targeted at
; a particular RISC-V FPU instruction.
-define bfloat @fadd_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fadd_s:
+define bfloat @fadd_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fadd_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -19,8 +19,8 @@ define bfloat @fadd_s(bfloat %a, bfloat %b) nounwind {
ret bfloat %1
}
-define bfloat @fsub_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fsub_s:
+define bfloat @fsub_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fsub_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -31,8 +31,8 @@ define bfloat @fsub_s(bfloat %a, bfloat %b) nounwind {
ret bfloat %1
}
-define bfloat @fmul_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fmul_s:
+define bfloat @fmul_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fmul_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -43,8 +43,8 @@ define bfloat @fmul_s(bfloat %a, bfloat %b) nounwind {
ret bfloat %1
}
-define bfloat @fdiv_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fdiv_s:
+define bfloat @fdiv_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fdiv_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -57,8 +57,8 @@ define bfloat @fdiv_s(bfloat %a, bfloat %b) nounwind {
declare bfloat @llvm.sqrt.bf16(bfloat)
-define bfloat @fsqrt_s(bfloat %a) nounwind {
-; CHECK-LABEL: fsqrt_s:
+define bfloat @fsqrt_bf16(bfloat %a) nounwind {
+; CHECK-LABEL: fsqrt_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fsqrt.s fa5, fa5
@@ -70,8 +70,8 @@ define bfloat @fsqrt_s(bfloat %a) nounwind {
declare bfloat @llvm.copysign.bf16(bfloat, bfloat)
-define bfloat @fsgnj_s(bfloat %a, bfloat %b) nounwind {
-; RV32IZFBFMIN-LABEL: fsgnj_s:
+define bfloat @fsgnj_bf16(bfloat %a, bfloat %b) nounwind {
+; RV32IZFBFMIN-LABEL: fsgnj_bf16:
; RV32IZFBFMIN: # %bb.0:
; RV32IZFBFMIN-NEXT: addi sp, sp, -16
; RV32IZFBFMIN-NEXT: fsh fa1, 12(sp)
@@ -91,7 +91,7 @@ define bfloat @fsgnj_s(bfloat %a, bfloat %b) nounwind {
; RV32IZFBFMIN-NEXT: addi sp, sp, 16
; RV32IZFBFMIN-NEXT: ret
;
-; RV64IZFBFMIN-LABEL: fsgnj_s:
+; RV64IZFBFMIN-LABEL: fsgnj_bf16:
; RV64IZFBFMIN: # %bb.0:
; RV64IZFBFMIN-NEXT: addi sp, sp, -16
; RV64IZFBFMIN-NEXT: fsh fa1, 8(sp)
@@ -114,8 +114,8 @@ define bfloat @fsgnj_s(bfloat %a, bfloat %b) nounwind {
ret bfloat %1
}
-define i32 @fneg_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fneg_s:
+define i32 @fneg_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fneg_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fadd.s fa5, fa5, fa5
@@ -135,8 +135,8 @@ define i32 @fneg_s(bfloat %a, bfloat %b) nounwind {
ret i32 %4
}
-define bfloat @fsgnjn_s(bfloat %a, bfloat %b) nounwind {
-; RV32IZFBFMIN-LABEL: fsgnjn_s:
+define bfloat @fsgnjn_bf16(bfloat %a, bfloat %b) nounwind {
+; RV32IZFBFMIN-LABEL: fsgnjn_bf16:
; RV32IZFBFMIN: # %bb.0:
; RV32IZFBFMIN-NEXT: addi sp, sp, -16
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
@@ -166,7 +166,7 @@ define bfloat @fsgnjn_s(bfloat %a, bfloat %b) nounwind {
; RV32IZFBFMIN-NEXT: addi sp, sp, 16
; RV32IZFBFMIN-NEXT: ret
;
-; RV64IZFBFMIN-LABEL: fsgnjn_s:
+; RV64IZFBFMIN-LABEL: fsgnjn_bf16:
; RV64IZFBFMIN: # %bb.0:
; RV64IZFBFMIN-NEXT: addi sp, sp, -16
; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
@@ -203,8 +203,8 @@ define bfloat @fsgnjn_s(bfloat %a, bfloat %b) nounwind {
declare bfloat @llvm.fabs.bf16(bfloat)
-define bfloat @fabs_s(bfloat %a, bfloat %b) nounwind {
-; RV32IZFBFMIN-LABEL: fabs_s:
+define bfloat @fabs_bf16(bfloat %a, bfloat %b) nounwind {
+; RV32IZFBFMIN-LABEL: fabs_bf16:
; RV32IZFBFMIN: # %bb.0:
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
@@ -220,7 +220,7 @@ define bfloat @fabs_s(bfloat %a, bfloat %b) nounwind {
; RV32IZFBFMIN-NEXT: fcvt.bf16.s fa0, fa5
; RV32IZFBFMIN-NEXT: ret
;
-; RV64IZFBFMIN-LABEL: fabs_s:
+; RV64IZFBFMIN-LABEL: fabs_bf16:
; RV64IZFBFMIN: # %bb.0:
; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa1
; RV64IZFBFMIN-NEXT: fcvt.s.bf16 fa4, fa0
@@ -243,8 +243,8 @@ define bfloat @fabs_s(bfloat %a, bfloat %b) nounwind {
declare bfloat @llvm.minnum.bf16(bfloat, bfloat)
-define bfloat @fmin_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fmin_s:
+define bfloat @fmin_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fmin_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -257,8 +257,8 @@ define bfloat @fmin_s(bfloat %a, bfloat %b) nounwind {
declare bfloat @llvm.maxnum.bf16(bfloat, bfloat)
-define bfloat @fmax_s(bfloat %a, bfloat %b) nounwind {
-; CHECK-LABEL: fmax_s:
+define bfloat @fmax_bf16(bfloat %a, bfloat %b) nounwind {
+; CHECK-LABEL: fmax_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -271,8 +271,8 @@ define bfloat @fmax_s(bfloat %a, bfloat %b) nounwind {
declare bfloat @llvm.fma.bf16(bfloat, bfloat, bfloat)
-define bfloat @fmadd_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fmadd_s:
+define bfloat @fmadd_bf16(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fmadd_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa2
; CHECK-NEXT: fcvt.s.bf16 fa4, fa1
@@ -284,8 +284,8 @@ define bfloat @fmadd_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %1
}
-define bfloat @fmsub_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fmsub_s:
+define bfloat @fmsub_bf16(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fmsub_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa2
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -307,8 +307,8 @@ define bfloat @fmsub_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %1
}
-define bfloat @fnmadd_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fnmadd_s:
+define bfloat @fnmadd_bf16(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fnmadd_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -406,8 +406,8 @@ define bfloat @fnmadd_nsz(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %neg
}
-define bfloat @fnmsub_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fnmsub_s:
+define bfloat @fnmsub_bf16(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fnmsub_bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -429,8 +429,8 @@ define bfloat @fnmsub_s(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %1
}
-define bfloat @fnmsub_s_2(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fnmsub_s_2:
+define bfloat @fnmsub_bf16_2(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fnmsub_bf16_2:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -452,8 +452,8 @@ define bfloat @fnmsub_s_2(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %1
}
-define bfloat @fmadd_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fmadd_s_contract:
+define bfloat @fmadd_bf16_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fmadd_bf16_contract:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa1
; CHECK-NEXT: fcvt.s.bf16 fa4, fa0
@@ -469,8 +469,8 @@ define bfloat @fmadd_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %2
}
-define bfloat @fmsub_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fmsub_s_contract:
+define bfloat @fmsub_bf16_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fmsub_bf16_contract:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa2
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -491,8 +491,8 @@ define bfloat @fmsub_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %2
}
-define bfloat @fnmadd_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fnmadd_s_contract:
+define bfloat @fnmadd_bf16_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fnmadd_bf16_contract:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fmv.w.x fa4, zero
@@ -526,8 +526,8 @@ define bfloat @fnmadd_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
ret bfloat %3
}
-define bfloat @fnmsub_s_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
-; CHECK-LABEL: fnmsub_s_contract:
+define bfloat @fnmsub_bf16_contract(bfloat %a, bfloat %b, bfloat %c) nounwind {
+; CHECK-LABEL: fnmsub_bf16_contract:
; CHECK: # %bb.0:
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK-NEXT: fmv.w.x fa4, zero
diff --git a/llvm/test/CodeGen/RISCV/half-arith.ll b/llvm/test/CodeGen/RISCV/half-arith.ll
index 653d8056d27b82..4c64e6c7a20906 100644
--- a/llvm/test/CodeGen/RISCV/half-arith.ll
+++ b/llvm/test/CodeGen/RISCV/half-arith.ll
@@ -25,18 +25,18 @@
; respectively. Some other half-*.ll files in this folder exercise LLVM IR
; instructions that don't directly match a RISC-V instruction.
-define half @fadd_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fadd_s:
+define half @fadd_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fadd_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fadd_s:
+; CHECKIZHINX-LABEL: fadd_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fadd_s:
+; RV32I-LABEL: fadd_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -62,7 +62,7 @@ define half @fadd_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fadd_s:
+; RV64I-LABEL: fadd_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -88,7 +88,7 @@ define half @fadd_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fadd_s:
+; CHECKIZFHMIN-LABEL: fadd_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -96,7 +96,7 @@ define half @fadd_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fadd_s:
+; CHECKIZHINXMIN-LABEL: fadd_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -107,18 +107,18 @@ define half @fadd_s(half %a, half %b) nounwind {
ret half %1
}
-define half @fsub_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fsub_s:
+define half @fsub_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fsub_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fsub.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fsub_s:
+; CHECKIZHINX-LABEL: fsub_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fsub.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fsub_s:
+; RV32I-LABEL: fsub_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -144,7 +144,7 @@ define half @fsub_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fsub_s:
+; RV64I-LABEL: fsub_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -170,7 +170,7 @@ define half @fsub_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fsub_s:
+; CHECKIZFHMIN-LABEL: fsub_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -178,7 +178,7 @@ define half @fsub_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fsub_s:
+; CHECKIZHINXMIN-LABEL: fsub_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -189,18 +189,18 @@ define half @fsub_s(half %a, half %b) nounwind {
ret half %1
}
-define half @fmul_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fmul_s:
+define half @fmul_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fmul_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmul.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmul_s:
+; CHECKIZHINX-LABEL: fmul_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmul.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmul_s:
+; RV32I-LABEL: fmul_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -226,7 +226,7 @@ define half @fmul_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmul_s:
+; RV64I-LABEL: fmul_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -252,7 +252,7 @@ define half @fmul_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmul_s:
+; CHECKIZFHMIN-LABEL: fmul_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -260,7 +260,7 @@ define half @fmul_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmul_s:
+; CHECKIZHINXMIN-LABEL: fmul_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -271,18 +271,18 @@ define half @fmul_s(half %a, half %b) nounwind {
ret half %1
}
-define half @fdiv_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fdiv_s:
+define half @fdiv_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fdiv_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fdiv.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fdiv_s:
+; CHECKIZHINX-LABEL: fdiv_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fdiv.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fdiv_s:
+; RV32I-LABEL: fdiv_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -308,7 +308,7 @@ define half @fdiv_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fdiv_s:
+; RV64I-LABEL: fdiv_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -334,7 +334,7 @@ define half @fdiv_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fdiv_s:
+; CHECKIZFHMIN-LABEL: fdiv_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -342,7 +342,7 @@ define half @fdiv_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fdiv_s:
+; CHECKIZHINXMIN-LABEL: fdiv_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -355,18 +355,18 @@ define half @fdiv_s(half %a, half %b) nounwind {
declare half @llvm.sqrt.f16(half)
-define half @fsqrt_s(half %a) nounwind {
-; CHECKIZFH-LABEL: fsqrt_s:
+define half @fsqrt_h(half %a) nounwind {
+; CHECKIZFH-LABEL: fsqrt_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fsqrt.h fa0, fa0
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fsqrt_s:
+; CHECKIZHINX-LABEL: fsqrt_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fsqrt.h a0, a0
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fsqrt_s:
+; RV32I-LABEL: fsqrt_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -379,7 +379,7 @@ define half @fsqrt_s(half %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fsqrt_s:
+; RV64I-LABEL: fsqrt_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
@@ -392,14 +392,14 @@ define half @fsqrt_s(half %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fsqrt_s:
+; CHECKIZFHMIN-LABEL: fsqrt_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fsqrt.s fa5, fa5
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fsqrt_s:
+; CHECKIZHINXMIN-LABEL: fsqrt_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fsqrt.s a0, a0
@@ -411,18 +411,18 @@ define half @fsqrt_s(half %a) nounwind {
declare half @llvm.copysign.f16(half, half)
-define half @fsgnj_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fsgnj_s:
+define half @fsgnj_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fsgnj_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fsgnj.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fsgnj_s:
+; CHECKIZHINX-LABEL: fsgnj_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fsgnj.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fsgnj_s:
+; RV32I-LABEL: fsgnj_h:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 1048568
; RV32I-NEXT: and a1, a1, a2
@@ -431,7 +431,7 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fsgnj_s:
+; RV64I-LABEL: fsgnj_h:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 1048568
; RV64I-NEXT: and a1, a1, a2
@@ -440,7 +440,7 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
;
-; RV32IZFHMIN-LABEL: fsgnj_s:
+; RV32IZFHMIN-LABEL: fsgnj_h:
; RV32IZFHMIN: # %bb.0:
; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: fsh fa1, 12(sp)
@@ -460,7 +460,7 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret
;
-; RV64IZFHMIN-LABEL: fsgnj_s:
+; RV64IZFHMIN-LABEL: fsgnj_h:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: addi sp, sp, -16
; RV64IZFHMIN-NEXT: fsh fa1, 8(sp)
@@ -480,7 +480,7 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV64IZFHMIN-NEXT: addi sp, sp, 16
; RV64IZFHMIN-NEXT: ret
;
-; RV32IZHINXMIN-LABEL: fsgnj_s:
+; RV32IZHINXMIN-LABEL: fsgnj_h:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
; RV32IZHINXMIN-NEXT: sh a1, 12(sp)
@@ -498,7 +498,7 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: ret
;
-; RV64IZHINXMIN-LABEL: fsgnj_s:
+; RV64IZHINXMIN-LABEL: fsgnj_h:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
; RV64IZHINXMIN-NEXT: sh a1, 8(sp)
@@ -521,22 +521,22 @@ define half @fsgnj_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
-define i32 @fneg_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fneg_s:
+define i32 @fneg_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fneg_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa5, fa0, fa0
; CHECKIZFH-NEXT: fneg.h fa4, fa5
; CHECKIZFH-NEXT: feq.h a0, fa5, fa4
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fneg_s:
+; CHECKIZHINX-LABEL: fneg_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, a0
; CHECKIZHINX-NEXT: fneg.h a1, a0
; CHECKIZHINX-NEXT: feq.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fneg_s:
+; RV32I-LABEL: fneg_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -567,7 +567,7 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fneg_s:
+; RV64I-LABEL: fneg_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -598,7 +598,7 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fneg_s:
+; CHECKIZFHMIN-LABEL: fneg_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fadd.s fa5, fa5, fa5
@@ -612,7 +612,7 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: feq.s a0, fa5, fa4
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fneg_s:
+; CHECKIZHINXMIN-LABEL: fneg_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, a0
@@ -632,20 +632,20 @@ define i32 @fneg_s(half %a, half %b) nounwind {
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
-define half @fsgnjn_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fsgnjn_s:
+define half @fsgnjn_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fsgnjn_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa5, fa0, fa1
; CHECKIZFH-NEXT: fsgnjn.h fa0, fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fsgnjn_s:
+; CHECKIZHINX-LABEL: fsgnjn_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a1, a0, a1
; CHECKIZHINX-NEXT: fsgnjn.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fsgnjn_s:
+; RV32I-LABEL: fsgnjn_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -684,7 +684,7 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fsgnjn_s:
+; RV64I-LABEL: fsgnjn_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -723,7 +723,7 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; RV32IZFHMIN-LABEL: fsgnjn_s:
+; RV32IZFHMIN-LABEL: fsgnjn_h:
; RV32IZFHMIN: # %bb.0:
; RV32IZFHMIN-NEXT: addi sp, sp, -16
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
@@ -753,7 +753,7 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV32IZFHMIN-NEXT: addi sp, sp, 16
; RV32IZFHMIN-NEXT: ret
;
-; RV64IZFHMIN-LABEL: fsgnjn_s:
+; RV64IZFHMIN-LABEL: fsgnjn_h:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: addi sp, sp, -16
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
@@ -783,7 +783,7 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV64IZFHMIN-NEXT: addi sp, sp, 16
; RV64IZFHMIN-NEXT: ret
;
-; RV32IZHINXMIN-LABEL: fsgnjn_s:
+; RV32IZHINXMIN-LABEL: fsgnjn_h:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: addi sp, sp, -16
; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
@@ -806,7 +806,7 @@ define half @fsgnjn_s(half %a, half %b) nounwind {
; RV32IZHINXMIN-NEXT: addi sp, sp, 16
; RV32IZHINXMIN-NEXT: ret
;
-; RV64IZHINXMIN-LABEL: fsgnjn_s:
+; RV64IZHINXMIN-LABEL: fsgnjn_h:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: addi sp, sp, -16
; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
@@ -838,22 +838,22 @@ declare half @llvm.fabs.f16(half)
; This function performs extra work to ensure that
; DAGCombiner::visitBITCAST doesn't replace the fabs with an and.
-define half @fabs_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fabs_s:
+define half @fabs_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fabs_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fadd.h fa5, fa0, fa1
; CHECKIZFH-NEXT: fabs.h fa4, fa5
; CHECKIZFH-NEXT: fadd.h fa0, fa4, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fabs_s:
+; CHECKIZHINX-LABEL: fabs_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, a1
; CHECKIZHINX-NEXT: fabs.h a1, a0
; CHECKIZHINX-NEXT: fadd.h a0, a1, a0
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fabs_s:
+; RV32I-LABEL: fabs_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -890,7 +890,7 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fabs_s:
+; RV64I-LABEL: fabs_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -927,7 +927,7 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; RV32IZFHMIN-LABEL: fabs_s:
+; RV32IZFHMIN-LABEL: fabs_h:
; RV32IZFHMIN: # %bb.0:
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa1
; RV32IZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -943,7 +943,7 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV32IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV32IZFHMIN-NEXT: ret
;
-; RV64IZFHMIN-LABEL: fabs_s:
+; RV64IZFHMIN-LABEL: fabs_h:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fcvt.s.h fa5, fa1
; RV64IZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -959,7 +959,7 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV64IZFHMIN-NEXT: fcvt.h.s fa0, fa5
; RV64IZFHMIN-NEXT: ret
;
-; RV32IZHINXMIN-LABEL: fabs_s:
+; RV32IZHINXMIN-LABEL: fabs_h:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: fcvt.s.h a1, a1
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -973,7 +973,7 @@ define half @fabs_s(half %a, half %b) nounwind {
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: ret
;
-; RV64IZHINXMIN-LABEL: fabs_s:
+; RV64IZHINXMIN-LABEL: fabs_h:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: fcvt.s.h a1, a1
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -994,18 +994,18 @@ define half @fabs_s(half %a, half %b) nounwind {
declare half @llvm.minnum.f16(half, half)
-define half @fmin_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fmin_s:
+define half @fmin_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fmin_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmin.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmin_s:
+; CHECKIZHINX-LABEL: fmin_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmin.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmin_s:
+; RV32I-LABEL: fmin_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -1031,7 +1031,7 @@ define half @fmin_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmin_s:
+; RV64I-LABEL: fmin_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -1057,7 +1057,7 @@ define half @fmin_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmin_s:
+; CHECKIZFHMIN-LABEL: fmin_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -1065,7 +1065,7 @@ define half @fmin_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmin_s:
+; CHECKIZHINXMIN-LABEL: fmin_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -1078,18 +1078,18 @@ define half @fmin_s(half %a, half %b) nounwind {
declare half @llvm.maxnum.f16(half, half)
-define half @fmax_s(half %a, half %b) nounwind {
-; CHECKIZFH-LABEL: fmax_s:
+define half @fmax_h(half %a, half %b) nounwind {
+; CHECKIZFH-LABEL: fmax_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmax.h fa0, fa0, fa1
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmax_s:
+; CHECKIZHINX-LABEL: fmax_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmax.h a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmax_s:
+; RV32I-LABEL: fmax_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
@@ -1115,7 +1115,7 @@ define half @fmax_s(half %a, half %b) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmax_s:
+; RV64I-LABEL: fmax_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -32
; RV64I-NEXT: sd ra, 24(sp) # 8-byte Folded Spill
@@ -1141,7 +1141,7 @@ define half @fmax_s(half %a, half %b) nounwind {
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmax_s:
+; CHECKIZFHMIN-LABEL: fmax_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -1149,7 +1149,7 @@ define half @fmax_s(half %a, half %b) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmax_s:
+; CHECKIZHINXMIN-LABEL: fmax_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -1162,18 +1162,18 @@ define half @fmax_s(half %a, half %b) nounwind {
declare half @llvm.fma.f16(half, half, half)
-define half @fmadd_s(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fmadd_s:
+define half @fmadd_h(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fmadd_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmadd_s:
+; CHECKIZHINX-LABEL: fmadd_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmadd_s:
+; RV32I-LABEL: fmadd_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -1206,7 +1206,7 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmadd_s:
+; RV64I-LABEL: fmadd_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -1239,7 +1239,7 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmadd_s:
+; CHECKIZFHMIN-LABEL: fmadd_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa2
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
@@ -1248,7 +1248,7 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmadd_s:
+; CHECKIZHINXMIN-LABEL: fmadd_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
@@ -1260,21 +1260,21 @@ define half @fmadd_s(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fmsub_s(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fmsub_s:
+define half @fmsub_h(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fmsub_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa5, fa2, fa5
; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmsub_s:
+; CHECKIZHINX-LABEL: fmsub_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
; CHECKIZHINX-NEXT: fmsub.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmsub_s:
+; RV32I-LABEL: fmsub_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -1318,7 +1318,7 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmsub_s:
+; RV64I-LABEL: fmsub_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -1362,7 +1362,7 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmsub_s:
+; CHECKIZFHMIN-LABEL: fmsub_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa2
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -1379,7 +1379,7 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmsub_s:
+; CHECKIZHINXMIN-LABEL: fmsub_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
; CHECKIZHINXMIN-NEXT: fadd.s a2, a2, zero
@@ -1398,8 +1398,8 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fnmadd_s(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmadd_s:
+define half @fnmadd_h(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmadd_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa4, fa0, fa5
@@ -1407,14 +1407,14 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmadd_s:
+; CHECKIZHINX-LABEL: fnmadd_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
; CHECKIZHINX-NEXT: fnmadd.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmadd_s:
+; RV32I-LABEL: fnmadd_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -1472,7 +1472,7 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmadd_s:
+; RV64I-LABEL: fnmadd_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -1530,7 +1530,7 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmadd_s:
+; CHECKIZFHMIN-LABEL: fnmadd_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -1553,7 +1553,7 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmadd_s:
+; CHECKIZHINXMIN-LABEL: fnmadd_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, zero
@@ -1578,8 +1578,8 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmadd_s_2:
+define half @fnmadd_h_2(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmadd_h_2:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa4, fa1, fa5
@@ -1587,14 +1587,14 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmadd_s_2:
+; CHECKIZHINX-LABEL: fnmadd_h_2:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
; CHECKIZHINX-NEXT: fnmadd.h a0, a1, a0, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmadd_s_2:
+; RV32I-LABEL: fnmadd_h_2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -1652,7 +1652,7 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmadd_s_2:
+; RV64I-LABEL: fnmadd_h_2:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -1710,7 +1710,7 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmadd_s_2:
+; CHECKIZFHMIN-LABEL: fnmadd_h_2:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -1733,7 +1733,7 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmadd_s_2:
+; CHECKIZHINXMIN-LABEL: fnmadd_h_2:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fadd.s a1, a1, zero
@@ -1758,33 +1758,33 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
-; RV32IZFH-LABEL: fnmadd_s_3:
+define half @fnmadd_h_3(half %a, half %b, half %c) nounwind {
+; RV32IZFH-LABEL: fnmadd_h_3:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
; RV32IZFH-NEXT: fneg.h fa0, ft0
; RV32IZFH-NEXT: ret
;
-; RV64IZFH-LABEL: fnmadd_s_3:
+; RV64IZFH-LABEL: fnmadd_h_3:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
; RV64IZFH-NEXT: fneg.h fa0, ft0
; RV64IZFH-NEXT: ret
;
-; CHECKIZFH-LABEL: fnmadd_s_3:
+; CHECKIZFH-LABEL: fnmadd_h_3:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmadd.h fa5, fa0, fa1, fa2
; CHECKIZFH-NEXT: fneg.h fa0, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmadd_s_3:
+; CHECKIZHINX-LABEL: fnmadd_h_3:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: lui a1, 1048568
; CHECKIZHINX-NEXT: xor a0, a0, a1
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmadd_s_3:
+; RV32I-LABEL: fnmadd_h_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -1819,7 +1819,7 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmadd_s_3:
+; RV64I-LABEL: fnmadd_h_3:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -1854,7 +1854,7 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmadd_s_3:
+; CHECKIZFHMIN-LABEL: fnmadd_h_3:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa2
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa1
@@ -1867,7 +1867,7 @@ define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fmv.h.x fa0, a0
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmadd_s_3:
+; CHECKIZHINXMIN-LABEL: fnmadd_h_3:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
@@ -2004,21 +2004,21 @@ define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
ret half %neg
}
-define half @fnmsub_s(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmsub_s:
+define half @fnmsub_h(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmsub_h:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa5, fa0, fa5
; CHECKIZFH-NEXT: fnmsub.h fa0, fa5, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmsub_s:
+; CHECKIZHINX-LABEL: fnmsub_h:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
; CHECKIZHINX-NEXT: fnmsub.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmsub_s:
+; RV32I-LABEL: fnmsub_h:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2061,7 +2061,7 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmsub_s:
+; RV64I-LABEL: fnmsub_h:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2104,7 +2104,7 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmsub_s:
+; CHECKIZFHMIN-LABEL: fnmsub_h:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -2121,7 +2121,7 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmsub_s:
+; CHECKIZHINXMIN-LABEL: fnmsub_h:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, zero
@@ -2140,21 +2140,21 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmsub_s_2:
+define half @fnmsub_h_2(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmsub_h_2:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa5, fa1, fa5
; CHECKIZFH-NEXT: fnmsub.h fa0, fa5, fa0, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmsub_s_2:
+; CHECKIZHINX-LABEL: fnmsub_h_2:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
; CHECKIZHINX-NEXT: fnmsub.h a0, a1, a0, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmsub_s_2:
+; RV32I-LABEL: fnmsub_h_2:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2198,7 +2198,7 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmsub_s_2:
+; RV64I-LABEL: fnmsub_h_2:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2242,7 +2242,7 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmsub_s_2:
+; CHECKIZFHMIN-LABEL: fnmsub_h_2:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -2259,7 +2259,7 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmsub_s_2:
+; CHECKIZHINXMIN-LABEL: fnmsub_h_2:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fadd.s a1, a1, zero
@@ -2278,18 +2278,18 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
ret half %1
}
-define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fmadd_s_contract:
+define half @fmadd_h_contract(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fmadd_h_contract:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmadd.h fa0, fa0, fa1, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmadd_s_contract:
+; CHECKIZHINX-LABEL: fmadd_h_contract:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fmadd.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmadd_s_contract:
+; RV32I-LABEL: fmadd_h_contract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2327,7 +2327,7 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmadd_s_contract:
+; RV64I-LABEL: fmadd_h_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2365,7 +2365,7 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmadd_s_contract:
+; CHECKIZFHMIN-LABEL: fmadd_h_contract:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa1
; CHECKIZFHMIN-NEXT: fcvt.s.h fa4, fa0
@@ -2377,7 +2377,7 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmadd_s_contract:
+; CHECKIZHINXMIN-LABEL: fmadd_h_contract:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a1, a1
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
@@ -2393,21 +2393,21 @@ define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
ret half %2
}
-define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fmsub_s_contract:
+define half @fmsub_h_contract(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fmsub_h_contract:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa5, fa2, fa5
; CHECKIZFH-NEXT: fmsub.h fa0, fa0, fa1, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fmsub_s_contract:
+; CHECKIZHINX-LABEL: fmsub_h_contract:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a2, a2, zero
; CHECKIZHINX-NEXT: fmsub.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fmsub_s_contract:
+; RV32I-LABEL: fmsub_h_contract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2451,7 +2451,7 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fmsub_s_contract:
+; RV64I-LABEL: fmsub_h_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2495,7 +2495,7 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fmsub_s_contract:
+; CHECKIZFHMIN-LABEL: fmsub_h_contract:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa2
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -2511,7 +2511,7 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fmsub_s_contract:
+; CHECKIZHINXMIN-LABEL: fmsub_h_contract:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a2, a2
; CHECKIZHINXMIN-NEXT: fadd.s a2, a2, zero
@@ -2531,8 +2531,8 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
ret half %2
}
-define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmadd_s_contract:
+define half @fnmadd_h_contract(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmadd_h_contract:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa4, fa0, fa5
@@ -2541,7 +2541,7 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmadd.h fa0, fa4, fa3, fa5
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmadd_s_contract:
+; CHECKIZHINX-LABEL: fnmadd_h_contract:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
@@ -2549,7 +2549,7 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZHINX-NEXT: fnmadd.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmadd_s_contract:
+; RV32I-LABEL: fnmadd_h_contract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2610,7 +2610,7 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmadd_s_contract:
+; RV64I-LABEL: fnmadd_h_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2671,7 +2671,7 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmadd_s_contract:
+; CHECKIZFHMIN-LABEL: fnmadd_h_contract:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -2697,7 +2697,7 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmadd_s_contract:
+; CHECKIZHINXMIN-LABEL: fnmadd_h_contract:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, zero
@@ -2728,8 +2728,8 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
ret half %3
}
-define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
-; CHECKIZFH-LABEL: fnmsub_s_contract:
+define half @fnmsub_h_contract(half %a, half %b, half %c) nounwind {
+; CHECKIZFH-LABEL: fnmsub_h_contract:
; CHECKIZFH: # %bb.0:
; CHECKIZFH-NEXT: fmv.h.x fa5, zero
; CHECKIZFH-NEXT: fadd.h fa4, fa0, fa5
@@ -2737,14 +2737,14 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFH-NEXT: fnmsub.h fa0, fa4, fa5, fa2
; CHECKIZFH-NEXT: ret
;
-; CHECKIZHINX-LABEL: fnmsub_s_contract:
+; CHECKIZHINX-LABEL: fnmsub_h_contract:
; CHECKIZHINX: # %bb.0:
; CHECKIZHINX-NEXT: fadd.h a0, a0, zero
; CHECKIZHINX-NEXT: fadd.h a1, a1, zero
; CHECKIZHINX-NEXT: fnmsub.h a0, a0, a1, a2
; CHECKIZHINX-NEXT: ret
;
-; RV32I-LABEL: fnmsub_s_contract:
+; RV32I-LABEL: fnmsub_h_contract:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
@@ -2795,7 +2795,7 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
-; RV64I-LABEL: fnmsub_s_contract:
+; RV64I-LABEL: fnmsub_h_contract:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
@@ -2846,7 +2846,7 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
;
-; CHECKIZFHMIN-LABEL: fnmsub_s_contract:
+; CHECKIZFHMIN-LABEL: fnmsub_h_contract:
; CHECKIZFHMIN: # %bb.0:
; CHECKIZFHMIN-NEXT: fcvt.s.h fa5, fa0
; CHECKIZFHMIN-NEXT: fmv.w.x fa4, zero
@@ -2865,7 +2865,7 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; CHECKIZFHMIN-NEXT: fcvt.h.s fa0, fa5
; CHECKIZFHMIN-NEXT: ret
;
-; CHECKIZHINXMIN-LABEL: fnmsub_s_contract:
+; CHECKIZHINXMIN-LABEL: fnmsub_h_contract:
; CHECKIZHINXMIN: # %bb.0:
; CHECKIZHINXMIN-NEXT: fcvt.s.h a0, a0
; CHECKIZHINXMIN-NEXT: fadd.s a0, a0, zero
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