[llvm] ba3c1ed - [RISCV] Correct the scheduler class for FCVT_S_BF16. (#107028)

[via llvm-commits]

Author: Craig Topper
Date: 2024-09-02T18:36:01-07:00
New Revision: ba3c1edcc8cf96206df259bd07001fa7ee9957cb

URL: https://github.com/llvm/llvm-project/commit/ba3c1edcc8cf96206df259bd07001fa7ee9957cb
DIFF: https://github.com/llvm/llvm-project/commit/ba3c1edcc8cf96206df259bd07001fa7ee9957cb.diff

LOG: [RISCV] Correct the scheduler class for FCVT_S_BF16. (#107028)

Use FCvtF16ToF32 instead of FCvtF32ToF16.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index bf6272317fda4d..52c4ee01bd44ac 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -31,7 +31,7 @@ let Predicates = [HasStdExtZfbfmin] in {
 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
                   Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
 def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
-                  Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
+                  Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
 } // Predicates = [HasStdExtZfbfmin]
 
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