[llvm] [llvm][Mips] Bail on underaligned loads/stores in FastISel. (PR #106231)

[Alex Rønne Petersen via llvm-commits]

================
@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march mips -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS
+
+ at var = external global i32, align 1
+
+; FastISel should bail on the underaligned load and store.
+define dso_local ccc i32 @__start() {
+; MIPS-LABEL: __start:
----------------
alexrp wrote:

> I have a try this testcase with the current llvm without your patch. It can produce the same asm code.

Are you sure you invoked `llc` with the same flags?

```
$ git rev-parse HEAD
0ba006daf5d9f10017ba15b4287c272912a34d73
$ ./build/bin/llc repro.ll -march mips -fast-isel -relocation-model pic -o -
        .text
        .abicalls
        .section        .mdebug.abi32,"", at progbits
        .nan    legacy
        .text
        .file   "test.ll"
        .globl  __start                         # -- Begin function __start
        .p2align        2
        .type   __start, at function
        .set    nomicromips
        .set    nomips16
        .ent    __start
__start:                                # @__start
        .cfi_startproc
        .frame  $sp,0,$ra
        .mask   0x00000000,0
        .fmask  0x00000000,0
        .set    noreorder
        .set    nomacro
        .set    noat
# %bb.0:
        lui     $2, %hi(_gp_disp)
        addiu   $2, $2, %lo(_gp_disp)
        addu    $1, $2, $25
        lw      $2, %got(var)($1)
        lw      $2, 0($2)
        addiu   $3, $zero, 42
        lw      $1, %got(var)($1)
        jr      $ra
        sw      $3, 0($1)
        .set    at
        .set    macro
        .set    reorder
        .end    __start
$func_end0:
        .size   __start, ($func_end0)-__start
        .cfi_endproc
                                        # -- End function
        .section        ".note.GNU-stack","", at progbits
        .text
```

The `-relocation-model pic` is important; non-PIC will bail out of FastISel early.

> And MIPSr6 support misaligned memory accessing.
> So, we need to add a testcase for MIPSr6.

Good point - will do.

https://github.com/llvm/llvm-project/pull/106231