[llvm] [llvm][Mips] Bail on underaligned loads/stores in FastISel. (PR #106231)

[YunQiang Su via llvm-commits]

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@@ -0,0 +1,23 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc < %s -march mips -fast-isel -relocation-model pic | FileCheck %s -check-prefixes=MIPS
+
+ at var = external global i32, align 1
+
+; FastISel should bail on the underaligned load and store.
+define dso_local ccc i32 @__start() {
+; MIPS-LABEL: __start:
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wzssyqa wrote:

I have a try this testcase with the current llvm without your patch.
It can produce the same asm code.

https://github.com/llvm/llvm-project/pull/106231