[llvm] [LegalizeVectorOps] Defer UnrollVectorOp in ExpandFNEG to caller. (PR #106783)

[Craig Topper via llvm-commits]

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@@ -1773,16 +1776,16 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
   EVT IntVT = VT.changeVectorElementTypeToInteger();
 
   // FIXME: The FSUB check is here to force unrolling v1f64 vectors on AArch64.
-  if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) &&
-      TLI.isOperationLegalOrCustom(ISD::FSUB, VT)) {
-    SDLoc DL(Node);
-    SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
-    SDValue SignMask = DAG.getConstant(
-        APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
-    SDValue Xor = DAG.getNode(ISD::XOR, DL, IntVT, Cast, SignMask);
-    return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
-  }
-  return DAG.UnrollVectorOp(Node);
+  if (!TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) ||
+      !TLI.isOperationLegalOrCustom(ISD::FSUB, VT))
+    return SDValue();
+
+  SDLoc DL(Node);
+  SDValue Cast = DAG.getNode(ISD::BITCAST, DL, IntVT, Node->getOperand(0));
+  SDValue SignMask = DAG.getConstant(
+      APInt::getSignMask(IntVT.getScalarSizeInBits()), DL, IntVT);
+  SDValue Xor = DAG.getNode(ISD::XOR, DL, IntVT, Cast, SignMask);
+  return DAG.getNode(ISD::BITCAST, DL, VT, Xor);
----------------
topperc wrote:

LegalizeDAG and LegalizeVectorOps have no uses of `DAG.getBitcast(`, but do use `DAG.getNode(ISD::BITCAST,`

https://github.com/llvm/llvm-project/pull/106783