[llvm] [RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (PR #107011)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 2 12:46:33 PDT 2024
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/107011
>From a99e613e738ca97ebb89f65c1224100cfea2f9be Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Sep 2024 10:42:29 -0700
Subject: [PATCH 1/3] [RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce
isel patterns that emit two instructions.
Most of the test changes are because we aren't consistent about what
rounding mode to use for fcvt.s.bf16 instructions. See also #106948.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 31 +++++++++++++-
.../lib/Target/RISCV/RISCVInstrInfoZfbfmin.td | 10 -----
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 16 --------
llvm/test/CodeGen/RISCV/bfloat-convert.ll | 32 +++++++--------
.../test/CodeGen/RISCV/half-convert-strict.ll | 28 ++++++-------
llvm/test/CodeGen/RISCV/half-convert.ll | 24 +++++------
llvm/test/CodeGen/RISCV/half-round-conv.ll | 40 +++++++++----------
...fixed-vectors-vfptoi-constrained-sdnode.ll | 4 +-
8 files changed, 94 insertions(+), 91 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d02078372b24a2..7cc44b150b8fbd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -462,6 +462,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::bf16, Custom);
setOperationAction(ISD::FNEG, MVT::bf16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::bf16, Expand);
+ setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
}
if (Subtarget.hasStdExtZfhminOrZhinxmin()) {
@@ -480,6 +481,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FABS, MVT::f16, Custom);
setOperationAction(ISD::FNEG, MVT::f16, Custom);
setOperationAction(ISD::FCOPYSIGN, MVT::f16, Expand);
+ setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, XLenVT, Custom);
}
setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
@@ -592,9 +594,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::FP_TO_UINT_SAT, ISD::FP_TO_SINT_SAT}, XLenVT,
Custom);
+ // f16/bf16 require custom handling.
setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
- XLenVT, Legal);
+ XLenVT, Custom);
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
@@ -3068,6 +3071,30 @@ static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
return Res;
}
+static SDValue lowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
+ const RISCVSubtarget &Subtarget) {
+ bool IsStrict = Op->isStrictFPOpcode();
+ SDValue SrcVal = Op.getOperand(IsStrict ? 1 : 0);
+
+ // f16 conversions are promoted to f32 when Zfh/Zhinx are no supported.
+ if ((SrcVal.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) ||
+ SrcVal.getValueType() == MVT::bf16) {
+ SDLoc DL(Op);
+ if (IsStrict) {
+ SDValue Ext =
+ DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
+ {Op.getOperand(0), SrcVal});
+ return DAG.getNode(Op.getOpcode(), DL, {Op.getValueType(), MVT::Other},
+ {Ext.getValue(1), Ext.getValue(0)});
+ }
+ return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
+ DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, SrcVal));
+ }
+
+ // Other operations are legal.
+ return Op;
+}
+
static RISCVFPRndMode::RoundingMode matchRoundingOp(unsigned Opc) {
switch (Opc) {
case ISD::FROUNDEVEN:
@@ -6582,6 +6609,8 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
// the source. We custom-lower any conversions that do two hops into
// sequences.
MVT VT = Op.getSimpleValueType();
+ if (VT.isScalarInteger())
+ return lowerFP_TO_INT(Op, DAG, Subtarget);
if (!VT.isVector())
return Op;
SDLoc DL(Op);
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
index 88b66e7fc49aad..5fb376656968e1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -67,22 +67,12 @@ def : Pat<(riscv_fmv_x_signexth (bf16 FPR16:$src)), (FMV_X_H FPR16:$src)>;
} // Predicates = [HasStdExtZfbfmin]
let Predicates = [HasStdExtZfbfmin] in {
-// bf16->[u]int. Round-to-zero must be used for the f32->int step, the
-// rounding mode has no effect for bf16->f32.
-def : Pat<(i32 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i32 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
def : Pat<(bf16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(bf16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
}
let Predicates = [HasStdExtZfbfmin, IsRV64] in {
-// bf16->[u]int64. Round-to-zero must be used for the f32->int step, the
-// rounding mode has no effect for bf16->f32.
-def : Pat<(i64 (any_fp_to_sint (bf16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i64 (any_fp_to_uint (bf16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_BF16 $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->bf16. Match GCC and default to using dynamic rounding mode.
def : Pat<(bf16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(bf16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_BF16_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index d60cf33567d6d0..441d95f8f95a1c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -601,40 +601,24 @@ def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H
} // Predicates = [HasStdExtZhinxmin, HasStdExtZdinx, IsRV64]
let Predicates = [HasStdExtZfhmin, NoStdExtZfh] in {
-// half->[u]int. Round-to-zero must be used.
-def : Pat<(i32 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_W_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i32 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_WU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->half. Match GCC and default to using dynamic rounding mode.
def : Pat<(f16 (any_sint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(f16 (any_uint_to_fp (i32 GPR:$rs1))), (FCVT_H_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh]
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx] in {
-// half->[u]int. Round-to-zero must be used.
-def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->half. Match GCC and default to using dynamic rounding mode.
def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_W_INX $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_WU_INX $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx]
let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
-// half->[u]int64. Round-to-zero must be used.
-def : Pat<(i64 (any_fp_to_sint (f16 FPR16:$rs1))), (FCVT_L_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i64 (any_fp_to_uint (f16 FPR16:$rs1))), (FCVT_LU_S (FCVT_S_H $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
def : Pat<(f16 (any_sint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(f16 (any_uint_to_fp (i64 GPR:$rs1))), (FCVT_H_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
} // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
-// half->[u]int64. Round-to-zero must be used.
-def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1, FRM_RNE), FRM_RTZ)>;
-
// [u]int->fp. Match GCC and default to using dynamic rounding mode.
def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_L_INX $rs1, FRM_DYN), FRM_DYN)>;
def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_LU_INX $rs1, FRM_DYN), FRM_DYN)>;
diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
index 6d90def954bdb0..55c8ed04bfb172 100644
--- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll
+++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
@@ -18,7 +18,7 @@
define i16 @fcvt_si_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
@@ -32,7 +32,7 @@ define i16 @fcvt_si_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -120,8 +120,8 @@ declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
-; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_ui_bf16:
@@ -134,8 +134,8 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
-; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
; RV64ID-LABEL: fcvt_ui_bf16:
@@ -206,7 +206,7 @@ declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
define i32 @fcvt_w_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
@@ -288,7 +288,7 @@ declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
@@ -320,7 +320,7 @@ define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: seqz a1, a0
; CHECK32ZFBFMIN-NEXT: add a0, a0, a1
@@ -438,7 +438,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -625,7 +625,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -1470,7 +1470,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind
define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
@@ -1484,7 +1484,7 @@ define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
@@ -1572,8 +1572,8 @@ declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
; CHECK32ZFBFMIN: # %bb.0:
-; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
-; CHECK32ZFBFMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
+; CHECK32ZFBFMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32ZFBFMIN-NEXT: ret
;
; RV32ID-LABEL: fcvt_wu_s_i8:
@@ -1586,7 +1586,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
;
; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
; CHECK64ZFBFMIN: # %bb.0:
-; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT: fcvt.s.bf16 fa5, fa0
; CHECK64ZFBFMIN-NEXT: fcvt.lu.s a0, fa5, rtz
; CHECK64ZFBFMIN-NEXT: ret
;
diff --git a/llvm/test/CodeGen/RISCV/half-convert-strict.ll b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
index 8f88a4c570ea05..47d7064404ac75 100644
--- a/llvm/test/CodeGen/RISCV/half-convert-strict.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert-strict.ll
@@ -136,78 +136,78 @@ declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
define i16 @fcvt_ui_h(half %a) nounwind strictfp {
; RV32IZFH-LABEL: fcvt_ui_h:
; RV32IZFH: # %bb.0:
-; RV32IZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcvt_ui_h:
; RV64IZFH: # %bb.0:
-; RV64IZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: fcvt_ui_h:
; RV32IZHINX: # %bb.0:
-; RV32IZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rtz
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: fcvt_ui_h:
; RV64IZHINX: # %bb.0:
-; RV64IZHINX-NEXT: fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rtz
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: fcvt_ui_h:
; RV32IDZFH: # %bb.0:
-; RV32IDZFH-NEXT: fcvt.wu.h a0, fa0, rtz
+; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rtz
; RV32IDZFH-NEXT: ret
;
; RV64IDZFH-LABEL: fcvt_ui_h:
; RV64IDZFH: # %bb.0:
-; RV64IDZFH-NEXT: fcvt.lu.h a0, fa0, rtz
+; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rtz
; RV64IDZFH-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
; RV32IZDINXZHINX: # %bb.0:
-; RV32IZDINXZHINX-NEXT: fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rtz
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
; RV64IZDINXZHINX: # %bb.0:
-; RV64IZDINXZHINX-NEXT: fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rtz
; RV64IZDINXZHINX-NEXT: ret
;
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
+; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: ret
;
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict")
ret i16 %1
diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll
index 48bfe1c37c625c..09da373f717d46 100644
--- a/llvm/test/CodeGen/RISCV/half-convert.ll
+++ b/llvm/test/CodeGen/RISCV/half-convert.ll
@@ -672,37 +672,37 @@ define i16 @fcvt_ui_h(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
; CHECK64-IZFHMIN: # %bb.0:
; CHECK64-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK64-IZFHMIN-NEXT: fcvt.lu.s a0, fa5, rtz
+; CHECK64-IZFHMIN-NEXT: fcvt.l.s a0, fa5, rtz
; CHECK64-IZFHMIN-NEXT: ret
;
; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZHINXMIN: # %bb.0:
; CHECK64-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK64-IZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZHINXMIN-NEXT: ret
;
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
; CHECK64-IZDINXZHINXMIN: # %bb.0:
; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rtz
; CHECK64-IZDINXZHINXMIN-NEXT: ret
%1 = fptoui half %a to i16
ret i16 %1
@@ -6808,7 +6808,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i16:
@@ -6820,7 +6820,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i16:
@@ -6832,7 +6832,7 @@ define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
@@ -7759,7 +7759,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZFHMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZFHMIN: # %bb.0:
; CHECK32-IZFHMIN-NEXT: fcvt.s.h fa5, fa0
-; CHECK32-IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; CHECK32-IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; CHECK32-IZFHMIN-NEXT: ret
;
; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i8:
@@ -7771,7 +7771,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZHINXMIN: # %bb.0:
; CHECK32-IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZHINXMIN-NEXT: ret
;
; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i8:
@@ -7783,7 +7783,7 @@ define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
; CHECK32-IZDINXZHINXMIN: # %bb.0:
; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
-; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; CHECK32-IZDINXZHINXMIN-NEXT: ret
;
; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
diff --git a/llvm/test/CodeGen/RISCV/half-round-conv.ll b/llvm/test/CodeGen/RISCV/half-round-conv.ll
index 173164db5b7807..2a1e0cfdda83e3 100644
--- a/llvm/test/CodeGen/RISCV/half-round-conv.ll
+++ b/llvm/test/CodeGen/RISCV/half-round-conv.ll
@@ -509,7 +509,7 @@ define zeroext i8 @test_floor_ui8(half %x) {
; RV32IZFHMIN-NEXT: .LBB4_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_ui8:
@@ -544,7 +544,7 @@ define zeroext i8 @test_floor_ui8(half %x) {
; RV32IZHINXMIN-NEXT: .LBB4_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_ui8:
@@ -624,7 +624,7 @@ define zeroext i16 @test_floor_ui16(half %x) {
; RV32IZFHMIN-NEXT: .LBB5_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_floor_ui16:
@@ -659,7 +659,7 @@ define zeroext i16 @test_floor_ui16(half %x) {
; RV32IZHINXMIN-NEXT: .LBB5_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_floor_ui16:
@@ -1383,7 +1383,7 @@ define zeroext i8 @test_ceil_ui8(half %x) {
; RV32IZFHMIN-NEXT: .LBB12_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_ui8:
@@ -1418,7 +1418,7 @@ define zeroext i8 @test_ceil_ui8(half %x) {
; RV32IZHINXMIN-NEXT: .LBB12_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_ui8:
@@ -1498,7 +1498,7 @@ define zeroext i16 @test_ceil_ui16(half %x) {
; RV32IZFHMIN-NEXT: .LBB13_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_ceil_ui16:
@@ -1533,7 +1533,7 @@ define zeroext i16 @test_ceil_ui16(half %x) {
; RV32IZHINXMIN-NEXT: .LBB13_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_ceil_ui16:
@@ -2257,7 +2257,7 @@ define zeroext i8 @test_trunc_ui8(half %x) {
; RV32IZFHMIN-NEXT: .LBB20_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_ui8:
@@ -2292,7 +2292,7 @@ define zeroext i8 @test_trunc_ui8(half %x) {
; RV32IZHINXMIN-NEXT: .LBB20_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_ui8:
@@ -2372,7 +2372,7 @@ define zeroext i16 @test_trunc_ui16(half %x) {
; RV32IZFHMIN-NEXT: .LBB21_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_trunc_ui16:
@@ -2407,7 +2407,7 @@ define zeroext i16 @test_trunc_ui16(half %x) {
; RV32IZHINXMIN-NEXT: .LBB21_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_trunc_ui16:
@@ -3131,7 +3131,7 @@ define zeroext i8 @test_round_ui8(half %x) {
; RV32IZFHMIN-NEXT: .LBB28_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_ui8:
@@ -3166,7 +3166,7 @@ define zeroext i8 @test_round_ui8(half %x) {
; RV32IZHINXMIN-NEXT: .LBB28_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_ui8:
@@ -3246,7 +3246,7 @@ define zeroext i16 @test_round_ui16(half %x) {
; RV32IZFHMIN-NEXT: .LBB29_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_round_ui16:
@@ -3281,7 +3281,7 @@ define zeroext i16 @test_round_ui16(half %x) {
; RV32IZHINXMIN-NEXT: .LBB29_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_round_ui16:
@@ -4005,7 +4005,7 @@ define zeroext i8 @test_roundeven_ui8(half %x) {
; RV32IZFHMIN-NEXT: .LBB36_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_ui8:
@@ -4040,7 +4040,7 @@ define zeroext i8 @test_roundeven_ui8(half %x) {
; RV32IZHINXMIN-NEXT: .LBB36_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_ui8:
@@ -4120,7 +4120,7 @@ define zeroext i16 @test_roundeven_ui16(half %x) {
; RV32IZFHMIN-NEXT: .LBB37_2:
; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5
; RV32IZFHMIN-NEXT: fcvt.s.h fa5, fa5
-; RV32IZFHMIN-NEXT: fcvt.wu.s a0, fa5, rtz
+; RV32IZFHMIN-NEXT: fcvt.w.s a0, fa5, rtz
; RV32IZFHMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: test_roundeven_ui16:
@@ -4155,7 +4155,7 @@ define zeroext i16 @test_roundeven_ui16(half %x) {
; RV32IZHINXMIN-NEXT: .LBB37_2:
; RV32IZHINXMIN-NEXT: fcvt.h.s a0, a0
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
-; RV32IZHINXMIN-NEXT: fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rtz
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: test_roundeven_ui16:
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
index 4334f293d1e858..5ac0d8d120cba5 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfptoi-constrained-sdnode.ll
@@ -55,14 +55,14 @@ define <1 x i7> @vfptoui_v1f16_v1i7(<1 x half> %va) strictfp {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV32-NEXT: vfmv.f.s fa5, v8
-; RV32-NEXT: fcvt.wu.h a0, fa5, rtz
+; RV32-NEXT: fcvt.w.h a0, fa5, rtz
; RV32-NEXT: ret
;
; RV64-LABEL: vfptoui_v1f16_v1i7:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 1, e16, m1, ta, ma
; RV64-NEXT: vfmv.f.s fa5, v8
-; RV64-NEXT: fcvt.lu.h a0, fa5, rtz
+; RV64-NEXT: fcvt.l.h a0, fa5, rtz
; RV64-NEXT: ret
%evec = call <1 x i7> @llvm.experimental.constrained.fptoui.v1i7.v1f16(<1 x half> %va, metadata !"fpexcept.strict")
ret <1 x i7> %evec
>From 1fde3ed7a47b4844defe76ba4ed3aa88dfad253d Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Sep 2024 12:38:38 -0700
Subject: [PATCH 2/3] fixup! Don't make STRICT_UINT_TO_FP/STRICT_SINT_TO_FP
custom.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7cc44b150b8fbd..61a5d0959b3ad0 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -595,9 +595,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Custom);
// f16/bf16 require custom handling.
- setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT,
- ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
+ setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
XLenVT, Custom);
+ setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
+ XLenVT, Legal);
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
>From 5e50093a91ad365534bdd541491966396734ae24 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Sep 2024 12:46:20 -0700
Subject: [PATCH 3/3] fixup! clang-format
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 61a5d0959b3ad0..a09e39f99d7d5a 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -595,10 +595,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
Custom);
// f16/bf16 require custom handling.
- setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT},
- XLenVT, Custom);
- setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP},
- XLenVT, Legal);
+ setOperationAction({ISD::STRICT_FP_TO_UINT, ISD::STRICT_FP_TO_SINT}, XLenVT,
+ Custom);
+ setOperationAction({ISD::STRICT_UINT_TO_FP, ISD::STRICT_SINT_TO_FP}, XLenVT,
+ Legal);
setOperationAction(ISD::GET_ROUNDING, XLenVT, Custom);
setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
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