[llvm] [ARM][Codegen] Fix vector data miscompilation in arm32be (PR #105519)

[via llvm-commits]

================
@@ -18601,7 +18588,6 @@ static SDValue PerformBITCASTCombine(SDNode *N,
   if ((Src.getOpcode() == ARMISD::VMOVIMM ||
        Src.getOpcode() == ARMISD::VMVNIMM ||
        Src.getOpcode() == ARMISD::VMOVFPIMM) &&
-      SrcVT.getScalarSizeInBits() <= DstVT.getScalarSizeInBits() &&
----------------
Zhenhang1213 wrote:

> I think this needs to be more restictive, not less restrictive. There are cases where it will convert `bitcast+vector_reg_cast+vmovimm` incorrectly as the bitcast needs to remain to keep the lane shuffling that is required.

so could I change
```
SrcVT.getScalarSizeInBits() <= DstVT.getScalarSizeInBits()
```
to 
```
SrcVT.getScalarSizeInBits() < DstVT.getScalarSizeInBits()
```

https://github.com/llvm/llvm-project/pull/105519