[llvm] [AArch64] Prevent generating tbl instruction instead of smull (PR #106375)

[Igor Kirillov via llvm-commits]

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@@ -16795,6 +16795,16 @@ bool AArch64TargetLowering::optimizeExtendOrTruncateConversion(
 
       DstTy = TruncDstType;
     }
+
+    // mul(zext(i8), sext) can be transformed into smull(zext, sext) when
+    // destination type is at least SrcWidth * 4, which is faster than using tbl
+    // instructions
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igogo-x86 wrote:

Is it? I might not understand something, but If SrcWidth is 8, DstWidth should be 32 or 64, meaning at least `SrcWidth*4`. "At most" would mean 8, 16, 32.

https://github.com/llvm/llvm-project/pull/106375