[llvm] [RISCV] Rename `vcix_state` register to `sf_vcix_state` (PR #106995)

[Brandon Wu via llvm-commits]

https://github.com/4vtomat created https://github.com/llvm/llvm-project/pull/106995

Since it's SiFive VCIX specific register, it's better to have a prefix
so that it's more understandable.


>From d26fde3aa27a1cbf280c42780b81913fe0f3b836 Mon Sep 17 00:00:00 2001
From: Brandon Wu <brandon.wu at sifive.com>
Date: Mon, 2 Sep 2024 07:06:09 -0700
Subject: [PATCH] [RISCV] Rename `vcix_state` register to `sf_vcix_state`

Since it's SiFive VCIX specific register, it's better to have a prefix
so that it's more understandable.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td  | 10 +++++-----
 llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp |  2 +-
 llvm/lib/Target/RISCV/RISCVRegisterInfo.td  |  4 ++--
 llvm/test/CodeGen/RISCV/rvv/copyprop.mir    |  2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
index 3b726e2e9bdc9b..3c1fb38349d5ca 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
@@ -308,7 +308,7 @@ class VPseudoVC_V_XVV<Operand OpClass, VReg RDClass, VReg RS2Class,
 multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
                        Operand OpClass = payload2> {
   let VLMul = m.value in {
-    let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
+    let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
       def "PseudoVC_" # NAME # "_SE_" # m.MX
         : VPseudoVC_X<OpClass, RS1Class>,
           Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
@@ -325,7 +325,7 @@ multiclass VPseudoVC_X<LMULInfo m, DAGOperand RS1Class,
 multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class,
                         Operand OpClass = payload2> {
   let VLMul = m.value in {
-    let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
+    let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
       def "PseudoVC_" # NAME # "_SE_" # m.MX
         : VPseudoVC_XV<OpClass, m.vrclass, RS1Class>,
           Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
@@ -342,7 +342,7 @@ multiclass VPseudoVC_XV<LMULInfo m, DAGOperand RS1Class,
 multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class,
                          Operand OpClass = payload2> {
   let VLMul = m.value in {
-    let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in {
+    let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in {
       def "PseudoVC_" # NAME # "_SE_" # m.MX
         : VPseudoVC_XVV<OpClass, m.vrclass, m.vrclass, RS1Class>,
           Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
@@ -359,12 +359,12 @@ multiclass VPseudoVC_XVV<LMULInfo m, DAGOperand RS1Class,
 multiclass VPseudoVC_XVW<LMULInfo m, DAGOperand RS1Class,
                          Operand OpClass = payload2> {
   let VLMul = m.value in {
-    let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in
+    let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in
     def "PseudoVC_" # NAME # "_SE_" # m.MX
       : VPseudoVC_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
         Sched<[!cast<SchedWrite>("WriteVC_" # NAME # "_" # m.MX)]>;
     let Constraints = "@earlyclobber $rd, $rd = $rs3" in {
-      let Defs = [VCIX_STATE], Uses = [VCIX_STATE] in
+      let Defs = [SF_VCIX_STATE], Uses = [SF_VCIX_STATE] in
       def "PseudoVC_V_" # NAME # "_SE_" # m.MX
         : VPseudoVC_V_XVV<OpClass, m.wvrclass, m.vrclass, RS1Class>,
           Sched<[!cast<SchedWrite>("WriteVC_V_" # NAME # "_" # m.MX)]>;
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 760d12103c36d4..701594c0fb05dc 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -145,7 +145,7 @@ BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   markSuperRegs(Reserved, RISCV::FFLAGS);
 
   // SiFive VCIX state registers.
-  markSuperRegs(Reserved, RISCV::VCIX_STATE);
+  markSuperRegs(Reserved, RISCV::SF_VCIX_STATE);
 
   if (MF.getFunction().getCallingConv() == CallingConv::GRAAL) {
     if (Subtarget.hasStdExtE())
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4d5c0a7bef9416..ce9f9e39154c2b 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -664,5 +664,5 @@ def FRM    : RISCVReg<0, "frm">;
 // Shadow Stack register
 def SSP    : RISCVReg<0, "ssp">;
 
-// Dummy VCIX state register
-def VCIX_STATE : RISCVReg<0, "vcix_state">;
+// Dummy SiFive VCIX state register
+def SF_VCIX_STATE : RISCVReg<0, "sf_vcix_state">;
diff --git a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
index 1718dc90eed49d..a9da6c305aac3c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
+++ b/llvm/test/CodeGen/RISCV/rvv/copyprop.mir
@@ -47,7 +47,7 @@ body:             |
     %22:vr = PseudoVMSNE_VI_M1 %3, 0, 1, 6 /* e64 */
     $v0 = COPY %22
     %25:vrnov0 = PseudoVMERGE_VIM_M1 undef $noreg, %17, -1, $v0, 1, 6 /* e64 */
-    %29:vr = PseudoVC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $vcix_state, implicit $vcix_state
+    %29:vr = PseudoVC_V_X_SE_M1 3, 31, %2, 1, 6 /* e64 */, implicit-def dead $sf_vcix_state, implicit $sf_vcix_state
     %30:vr = PseudoVMV_V_I_M1 undef $noreg, 0, 1, 6 /* e64 */, 0
     BGEU %1, $x0, %bb.2