[llvm] [RISCV] Added new register class GPRNoGPRS defined as substraction of GPRC sequences from GPR (PR #106974)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-risc-v

Author: Vladislav Belov (vbe-sc)

<details>
<summary>Changes</summary>

This patch adds new register class allowed to select general purpose registers that can not be used as operands of compressed instructions. It can be useful for some compiler routine and llvm-based RISC-V tools. 

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Full diff: https://github.com/llvm/llvm-project/pull/106974.diff


1 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVRegisterInfo.td (+3) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 4d5c0a7bef9416..63dcdf72552d5e 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -180,6 +180,9 @@ def GPRJALRNonX7 : GPRRegisterClass<(sub GPRJALR, X7)>;
 def GPRC : GPRRegisterClass<(add (sequence "X%u", 10, 15),
                                  (sequence "X%u", 8, 9))>;
 
+// The list of GPR registers not using with compressed instructions
+def GPRNoGPRC : GPRRegisterClass<(sub GPR, GPRC)>;
+
 // For indirect tail calls, we can't use callee-saved registers, as they are
 // restored to the saved value before the tail call, which would clobber a call
 // address. We shouldn't use x5 since that is a hint for to pop the return

``````````

</details>


https://github.com/llvm/llvm-project/pull/106974