[llvm] [DL] Invert `getTypeStoreSize` bytes-bits relationship to avoid `divideCeil` (PR #106757)

[via llvm-commits]

llvmbot wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-llvm-ir

Author: Antonio Frighetto (antoniofrighetto)

<details>
<summary>Changes</summary>

Change how `getTypeStoreSize` and `getTypeStoreSizeInBits` interact by first aligning the bit size to the nearest power of 2 boundary and then applying plain division to derive the byte size. This simplifies the calculation by avoiding possible overflow concerns in the first place.

---
Full diff: https://github.com/llvm/llvm-project/pull/106757.diff


1 Files Affected:

- (modified) llvm/include/llvm/IR/DataLayout.h (+6-3) 


``````````diff
diff --git a/llvm/include/llvm/IR/DataLayout.h b/llvm/include/llvm/IR/DataLayout.h
index 145f1a29c7dfb7..96e284726c7ad9 100644
--- a/llvm/include/llvm/IR/DataLayout.h
+++ b/llvm/include/llvm/IR/DataLayout.h
@@ -421,8 +421,8 @@ class DataLayout {
   ///
   /// For example, returns 5 for i36 and 10 for x86_fp80.
   TypeSize getTypeStoreSize(Type *Ty) const {
-    TypeSize BaseSize = getTypeSizeInBits(Ty);
-    return {divideCeil(BaseSize.getKnownMinValue(), 8), BaseSize.isScalable()};
+    TypeSize StoreSizeInBits = getTypeStoreSizeInBits(Ty);
+    return {StoreSizeInBits.getKnownMinValue() / 8, StoreSizeInBits.isScalable()};
   }
 
   /// Returns the maximum number of bits that may be overwritten by
@@ -433,7 +433,10 @@ class DataLayout {
   ///
   /// For example, returns 40 for i36 and 80 for x86_fp80.
   TypeSize getTypeStoreSizeInBits(Type *Ty) const {
-    return 8 * getTypeStoreSize(Ty);
+    TypeSize BaseSize = getTypeSizeInBits(Ty);
+    uint64_t AlignedSizeInBits =
+        alignToPowerOf2(BaseSize.getKnownMinValue(), sizeof(uint64_t));
+    return {AlignedSizeInBits, BaseSize.isScalable()};
   }
 
   /// Returns true if no extra padding bits are needed when storing the

``````````

</details>


https://github.com/llvm/llvm-project/pull/106757