[llvm] [ARM] Don't use -1 as invalid register number in assembly parser. (PR #106666)

[Sergei Barannikov via llvm-commits]

================
@@ -4634,7 +4633,7 @@ bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
     Reg = getDRegFromQReg(Reg);
     EReg = MRI->getEncodingValue(Reg);
     Registers.emplace_back(EReg, Reg);
-    ++Reg;
+    Reg = Reg + 1;
----------------
s-barannikov wrote:

> IIRC registers are emitted in the order they are defined in td

No, it seems it's not that simple. They're not sorted alphabetically either.


https://github.com/llvm/llvm-project/pull/106666