[llvm] [LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (PR #106652)
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 30 00:06:17 PDT 2024
================
@@ -1685,6 +1693,53 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
return DAG.UnrollVectorOp(Node);
}
+SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
+ EVT VT = Node->getValueType(0);
+ EVT IntVT = VT.changeVectorElementTypeToInteger();
+
+ // FIXME: We shouldn't restrict this to scalable vectors.
+ if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) && VT.isScalableVector()) {
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topperc wrote:
Yes. Thanks
https://github.com/llvm/llvm-project/pull/106652
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