[llvm] [LegalizeDAG][RISCV] Don't promote f16 vector ISD::FNEG/FABS/FCOPYSIGN to f32 when we don't have Zvfh. (PR #106652)

[Luke Lau via llvm-commits]

================
@@ -1685,6 +1693,53 @@ SDValue VectorLegalizer::ExpandFNEG(SDNode *Node) {
   return DAG.UnrollVectorOp(Node);
 }
 
+SDValue VectorLegalizer::ExpandFABS(SDNode *Node) {
+  EVT VT = Node->getValueType(0);
+  EVT IntVT = VT.changeVectorElementTypeToInteger();
+
+  // FIXME: We shouldn't restrict this to scalable vectors.
+  if (TLI.isOperationLegalOrCustom(ISD::XOR, IntVT) && VT.isScalableVector()) {
----------------
lukel97 wrote:

Should this be checking if ISD::AND is legal

https://github.com/llvm/llvm-project/pull/106652