[llvm] [RISCV][SiFive7] Change `Latency` of VCIX to the default (PR #106497)

[Michal Terepeta via llvm-commits]

https://github.com/michalt updated https://github.com/llvm/llvm-project/pull/106497

>From a3727d46ae70e0a65082dee355b152446bebcfe2 Mon Sep 17 00:00:00 2001
From: Michal Terepeta <michalt at google.com>
Date: Thu, 29 Aug 2024 08:10:33 +0200
Subject: [PATCH 1/3] [RISCV][SiFive7] Change `Latency` of VCIX to the default

Currently we multiply the default (`SiFive7GetCyclesDefault`) by 10, but
this turns out to be both surprising to our users and leads to worse
codegen in most cases. I think it's more natural to just keep the
default.

In the end the right solution is probably to have a separate scheduling
model for a particular VCIX coprocessor.
---
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 0b0ac0c368d070..72560284dde2f5 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -973,7 +973,7 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 foreach mx = SchedMxList in {
   defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
-  let Latency = !mul(Cycles, 10),
+  let Latency = Cycles,
       AcquireAtCycles = [0, 1],
       ReleaseAtCycles = [1, !add(1, Cycles)] in {
     defm "" : LMULWriteResMX<"WriteVC_V_I",   [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>;

>From 60644c9ee2cd0edabcbe5f6918e0284e6c585aca Mon Sep 17 00:00:00 2001
From: Michal Terepeta <michalt at google.com>
Date: Thu, 29 Aug 2024 08:34:15 +0200
Subject: [PATCH 2/3] fixup! [RISCV][SiFive7] Change `Latency` of VCIX to the
 default

update comment
---
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 72560284dde2f5..637cb5bf0f42e7 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -966,8 +966,8 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 // VCIX
 //
 // In principle we don't know the latency of any VCIX instructions. But instead
-// of taking the default of 1, which can lead to issues [1], we assume that they
-// have a fairly high latency.
+// of taking the default of 1, which can lead to issues [1], we use the default
+// latency provided by `SiFive7GetCyclesDefault`.
 //
 // [1] https://github.com/llvm/llvm-project/issues/83391
 foreach mx = SchedMxList in {

>From 400bd24d5813bcd73b707e08d2f3879146ca4260 Mon Sep 17 00:00:00 2001
From: Michal Terepeta <michalt at google.com>
Date: Fri, 30 Aug 2024 07:25:30 +0200
Subject: [PATCH 3/3] fixup! [RISCV][SiFive7] Change `Latency` of VCIX to the
 default

expand the comment
---
 llvm/lib/Target/RISCV/RISCVSchedSiFive7.td | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 637cb5bf0f42e7..71d8cda9d85c34 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -965,9 +965,12 @@ def : InstRW<[WriteIALU], (instrs COPY)>;
 
 // VCIX
 //
-// In principle we don't know the latency of any VCIX instructions. But instead
-// of taking the default of 1, which can lead to issues [1], we use the default
-// latency provided by `SiFive7GetCyclesDefault`.
+// In principle we don't know the latency of any VCIX instructions (they
+// depends on a particular coprocessor implementation). However, the default
+// latency of 1 can lead to issues [1]. So instead we set the latency to the
+// default provided by `SiFive7GetCyclesDefault`. This is still not accurate
+// and can lead to suboptimal codegen, but should hopefully be a better
+// starting point.
 //
 // [1] https://github.com/llvm/llvm-project/issues/83391
 foreach mx = SchedMxList in {