[llvm] [DSE] Don't shrink memory intrinsic if its liable to make codegen worse (PR #106425)

[Florian Hahn via llvm-commits]

fhahn wrote:

> > * It looks like getLoadStoreVecRegBitWidth defaults to 128 and is not overridden on most targets. In the context of this patch, it will be misleading for any (sub-)targets without vectors. 128 bit is a good default assumption for a target that has vectors, but not for a scalar-only target.
> 
> Do you know how to test if a target supports vectors? I don't see any obvious knob.

Might be worth to try 

```
  /// \return The width of the largest scalar or vector register type.                                                                    <<<
  TypeSize getRegisterBitWidth(RegisterKind K) const;
```

https://github.com/llvm/llvm-project/pull/106425