[compiler-rt] [compiler-rt][RISCV][NFC] Update code_model with latest spec (PR #106498)
Piyou Chen via llvm-commits
llvm-commits at lists.llvm.org
Wed Aug 28 23:23:17 PDT 2024
https://github.com/BeMg created https://github.com/llvm/llvm-project/pull/106498
This patch updates the following symbol:
```
mVendorID -> mvendorid
mArchID -> marchid
mImplID -> mimpid
```
>From 9d2ee60e9ab2ea6b15bcf1cd318a7f69c09d2ba9 Mon Sep 17 00:00:00 2001
From: Piyou Chen <piyou.chen at sifive.com>
Date: Wed, 28 Aug 2024 23:20:59 -0700
Subject: [PATCH] [compiler-rt][RISCV] Update code_model with latest spec
---
compiler-rt/lib/builtins/cpu_model/riscv.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/compiler-rt/lib/builtins/cpu_model/riscv.c b/compiler-rt/lib/builtins/cpu_model/riscv.c
index 987812c18fa792..85b24ab8f43bc1 100644
--- a/compiler-rt/lib/builtins/cpu_model/riscv.c
+++ b/compiler-rt/lib/builtins/cpu_model/riscv.c
@@ -21,9 +21,9 @@ struct {
} __riscv_vendor_feature_bits __attribute__((visibility("hidden"), nocommon));
struct {
- unsigned mVendorID;
- unsigned mArchID;
- unsigned mImplID;
+ unsigned mvendorid;
+ unsigned marchid;
+ unsigned mimpid;
} __riscv_cpu_model __attribute__((visibility("hidden"), nocommon));
// NOTE: Should sync-up with RISCVFeatures.td
@@ -250,9 +250,9 @@ static void initRISCVFeature(struct riscv_hwprobe Hwprobes[]) {
// This unsets all extension bitmask bits.
// Init VendorID, ArchID, ImplID
- __riscv_cpu_model.mVendorID = Hwprobes[2].value;
- __riscv_cpu_model.mArchID = Hwprobes[3].value;
- __riscv_cpu_model.mImplID = Hwprobes[4].value;
+ __riscv_cpu_model.mvendorid = Hwprobes[2].value;
+ __riscv_cpu_model.marchid = Hwprobes[3].value;
+ __riscv_cpu_model.mimpid = Hwprobes[4].value;
// Init standard extension
// TODO: Maybe Extension implied generate from tablegen?
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