[llvm] 89bbcbe - [PowerPC] fix legalization crash (#105563)

[via llvm-commits]

Author: RolandF77
Date: 2024-08-28T11:22:23-04:00
New Revision: 89bbcbe285eee1287a9ea21b92e4b3d307464d44

URL: https://github.com/llvm/llvm-project/commit/89bbcbe285eee1287a9ea21b92e4b3d307464d44
DIFF: https://github.com/llvm/llvm-project/commit/89bbcbe285eee1287a9ea21b92e4b3d307464d44.diff

LOG: [PowerPC] fix legalization crash (#105563)

If v2i64 scalar_to_vector is made custom, llc can crash in certain
legalization cases where v2i64 vectors are injected, even if they
weren't otherwise present. The code generated would be fine, but that
operation is not handled in ReplaceNodeResults. Add handling.

Added: 
    llvm/test/CodeGen/PowerPC/custom-stov.ll

Modified: 
    llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index efabfa0b511a6e..83772200ade5c7 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -12027,6 +12027,12 @@ void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
       Results.push_back(Lowered);
     return;
   }
+  case ISD::SCALAR_TO_VECTOR: {
+    SDValue Lowered = LowerSCALAR_TO_VECTOR(SDValue(N, 0), DAG);
+    if (Lowered)
+      Results.push_back(Lowered);
+    return;
+  }
   case ISD::FSHL:
   case ISD::FSHR:
     // Don't handle funnel shifts here.

diff  --git a/llvm/test/CodeGen/PowerPC/custom-stov.ll b/llvm/test/CodeGen/PowerPC/custom-stov.ll
new file mode 100644
index 00000000000000..0642fa900b0e50
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/custom-stov.ll
@@ -0,0 +1,55 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mcpu=ppc64 -mtriple=powerpc64-unknown-linux-gnu \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr \
+; RUN:     < %s | FileCheck %s
+
+define void @_blah() {
+; CHECK-LABEL: _blah:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    li r3, 0
+; CHECK-NEXT:    li r4, 15
+; CHECK-NEXT:    lvx v3, 0, r4
+; CHECK-NEXT:    addi r5, r1, -64
+; CHECK-NEXT:    lvx v4, 0, r3
+; CHECK-NEXT:    lvsl v2, 0, r3
+; CHECK-NEXT:    vperm v2, v4, v3, v2
+; CHECK-NEXT:    lwz r4, 16(0)
+; CHECK-NEXT:    stvx v2, 0, r5
+; CHECK-NEXT:    lhz r5, -64(r1)
+; CHECK-NEXT:    lhz r6, -58(r1)
+; CHECK-NEXT:    lhz r7, -52(r1)
+; CHECK-NEXT:    sth r4, -34(r1)
+; CHECK-NEXT:    sth r3, -36(r1)
+; CHECK-NEXT:    sth r3, -40(r1)
+; CHECK-NEXT:    sth r3, -44(r1)
+; CHECK-NEXT:    sth r3, -48(r1)
+; CHECK-NEXT:    addi r3, r1, -48
+; CHECK-NEXT:    sth r7, -38(r1)
+; CHECK-NEXT:    sth r6, -42(r1)
+; CHECK-NEXT:    sth r5, -46(r1)
+; CHECK-NEXT:    lvx v2, 0, r3
+; CHECK-NEXT:    addi r3, r1, -32
+; CHECK-NEXT:    vsldoi v3, v2, v2, 8
+; CHECK-NEXT:    vmaxuw v2, v2, v3
+; CHECK-NEXT:    vspltw v3, v2, 1
+; CHECK-NEXT:    vmaxuw v2, v2, v3
+; CHECK-NEXT:    stvx v2, 0, r3
+; CHECK-NEXT:    lwz r3, -32(r1)
+; CHECK-NEXT:    cmplwi r3, 0
+; CHECK-NEXT:    blr
+entry:
+  %wide.vec904 = load <12 x i16>, ptr null, align 2
+  %strided.vec905 = shufflevector <12 x i16> %wide.vec904, <12 x i16> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 6, i32 9>
+  %0 = zext <4 x i16> %strided.vec905 to <4 x i32>
+  %1 = tail call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> %0)
+  %cmp55.not823 = icmp ugt i32 1, %1
+  br i1 %cmp55.not823, label %for.cond.cleanup56, label %for.body57.lr.ph
+
+for.body57.lr.ph:                                 ; preds = %entry
+  ret void
+
+for.cond.cleanup56:                               ; preds = %entry
+  ret void
+}
+
+declare i32 @llvm.vector.reduce.umax.v4i32(<4 x i32>)