[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

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git-clang-format --diff 4bf68aaca2ec11ffde3ee4c30e9761a144434a92 cdd3b1034e8aec7bdfb0f4c5d840ab3a9f689285 --extensions cpp -- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
index 2d63ffee38..11b48e8c1d 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -1195,7 +1195,8 @@ void AMDGPUTargetLowering::analyzeFormalArgumentsCompute(
 
       if (NumRegs == 1) {
         // This argument is not split, so the IR type is the memory type.
-        if (ArgVT.isExtended() || (ArgVT.isVector() && !ArgVT.isPow2VectorType())) {
+        if (ArgVT.isExtended() ||
+            (ArgVT.isVector() && !ArgVT.isPow2VectorType())) {
           // We have an extended type, like i24, so we should just use the
           // register type.
           MemVT = RegisterVT;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 7277bac973..9e2c7f22b1 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -2630,10 +2630,9 @@ static MVT getContainerForFixedLengthVector(const TargetLowering &TLI, MVT VT,
     // each fractional LMUL we support SEW between 8 and LMUL*ELEN.
     unsigned NumVLSElts = VT.getVectorNumElements();
     if (!isPowerOf2_32(NumVLSElts))
-       NumVLSElts = llvm::NextPowerOf2 (NumVLSElts);
+      NumVLSElts = llvm::NextPowerOf2(NumVLSElts);
 
-    unsigned NumElts =
-        (NumVLSElts * RISCV::RVVBitsPerBlock) / MinVLen;
+    unsigned NumElts = (NumVLSElts * RISCV::RVVBitsPerBlock) / MinVLen;
     NumElts = std::max(NumElts, RISCV::RVVBitsPerBlock / MaxELen);
 
     return MVT::getScalableVectorVT(EltVT, NumElts);
@@ -3583,7 +3582,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
     // codegen across RV32 and RV64.
     unsigned NumViaIntegerBits = std::clamp(NumElts, 8u, Subtarget.getXLen());
     if (!isPowerOf2_32(NumViaIntegerBits))
-       NumViaIntegerBits = llvm::NextPowerOf2 (NumViaIntegerBits);
+      NumViaIntegerBits = llvm::NextPowerOf2(NumViaIntegerBits);
     NumViaIntegerBits = std::min(NumViaIntegerBits, Subtarget.getELen());
     // If we have to use more than one INSERT_VECTOR_ELT then this
     // optimization is likely to increase code size; avoid peforming it in
@@ -3627,7 +3626,7 @@ static SDValue lowerBuildVectorOfConstants(SDValue Op, SelectionDAG &DAG,
       // If we're producing a smaller vector than our minimum legal integer
       // type, bitcast to the equivalent (known-legal) mask type, and extract
       // our final mask.
-      if (IntegerViaVecVT == MVT::v1i8){
+      if (IntegerViaVecVT == MVT::v1i8) {
         assert(IntegerViaVecVT == MVT::v1i8 && "Unexpected mask vector type");
         Vec = DAG.getBitcast(MVT::v8i1, Vec);
         Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VT, Vec,

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https://github.com/llvm/llvm-project/pull/97010