[llvm] [RISCV] Allow non-power-of-2 vectors for VLS code generation (PR #97010)

[Kito Cheng via llvm-commits]

kito-cheng wrote:

Rebase, got one more fail after rebase, however it's `CodeGen/AMDGPU/trunc-store.ll`, so I think it should be fine for now, and will fix that if we want to take this approach  

https://github.com/llvm/llvm-project/pull/97010