[llvm] [X86] Shrink width of masked loads/stores (PR #105451)
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Wed Aug 21 10:35:46 PDT 2024
goldsteinn wrote:
> Can we do the shrink in IR phase?
Probably, although I wasn't sure 1) the profitability on other arch 2) if it might mess up vectorization to have different sized vecs in the middle-end and 3) I wasn't 100% sure on the semantics, particularly: "Only the masked-on lanes of the vector need to be inbounds of an allocation (but all these lanes need to be inbounds of the same allocation)" I wasn't sure if we could gurantee the second point but I'm not an expert in the memory model.
https://github.com/llvm/llvm-project/pull/105451
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