[llvm] [LLVM][AArch64] Improve big endian code generation for SVE BITCASTs. (PR #104769)

[Eli Friedman via llvm-commits]

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@@ -6140,6 +6140,8 @@ SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
     break;
   case ISD::BSWAP:
     assert(VT.isInteger() && VT == N1.getValueType() && "Invalid BSWAP!");
+    if (VT.getScalarSizeInBits() == 8)
+      return N1;
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efriedma-quic wrote:

The scalarsize % 16 assumption is global throughout LLVM; I'd prefer not to add an exception if we don't need one.

https://github.com/llvm/llvm-project/pull/104769