[llvm] 69115cc - [AArch64] Use SelectionDAG::getSignedConstant/getAllOnesConstant.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 17 18:03:02 PDT 2024
Author: Craig Topper
Date: 2024-08-17T18:02:49-07:00
New Revision: 69115cce29d5dbbdacaa05aaedc89810aa58ef0c
URL: https://github.com/llvm/llvm-project/commit/69115cce29d5dbbdacaa05aaedc89810aa58ef0c
DIFF: https://github.com/llvm/llvm-project/commit/69115cce29d5dbbdacaa05aaedc89810aa58ef0c.diff
LOG: [AArch64] Use SelectionDAG::getSignedConstant/getAllOnesConstant.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index d9b0f083d469c..f5f9a62faa0f5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -913,7 +913,8 @@ bool AArch64DAGToDAGISel::SelectRDVLImm(SDValue N, SDValue &Imm) {
if ((MulImm % std::abs(Scale)) == 0) {
int64_t RDVLImm = MulImm / Scale;
if ((RDVLImm >= Low) && (RDVLImm <= High)) {
- Imm = CurDAG->getTargetConstant(RDVLImm, SDLoc(N), MVT::i32);
+ Imm = CurDAG->getSignedConstant(RDVLImm, SDLoc(N), MVT::i32,
+ /*isTarget=*/true);
return true;
}
}
@@ -4245,7 +4246,7 @@ bool AArch64DAGToDAGISel::SelectSVESignedArithImm(SDValue N, SDValue &Imm) {
int64_t ImmVal = CNode->getSExtValue();
SDLoc DL(N);
if (ImmVal >= -128 && ImmVal < 128) {
- Imm = CurDAG->getTargetConstant(ImmVal, DL, MVT::i32);
+ Imm = CurDAG->getSignedConstant(ImmVal, DL, MVT::i32, /*isTarget=*/true);
return true;
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 97fb2c5f55273..e1d265fdf0d1a 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -3970,9 +3970,9 @@ static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue SExt =
DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
DAG.getValueType(MVT::i16));
- Cmp = emitComparison(SExt, DAG.getConstant(ValueofRHS, dl,
- RHS.getValueType()),
- CC, dl, DAG);
+ Cmp = emitComparison(
+ SExt, DAG.getSignedConstant(ValueofRHS, dl, RHS.getValueType()), CC,
+ dl, DAG);
AArch64CC = changeIntCCToAArch64CC(CC);
}
}
@@ -4158,7 +4158,7 @@ SDValue AArch64TargetLowering::LowerXOR(SDValue Op, SelectionDAG &DAG) const {
FVal = Other;
TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,
- DAG.getConstant(-1ULL, dl, Other.getValueType()));
+ DAG.getAllOnesConstant(dl, Other.getValueType()));
return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,
CCVal, Cmp);
@@ -8966,7 +8966,8 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
// Each tail call may have to adjust the stack by a
diff erent amount, so
// this information must travel along with the operation for eventual
// consumption by emitEpilogue.
- Ops.push_back(DAG.getTargetConstant(FPDiff, DL, MVT::i32));
+ Ops.push_back(
+ DAG.getSignedConstant(FPDiff, DL, MVT::i32, /*isTarget=*/true));
}
if (CLI.PAI) {
@@ -11144,7 +11145,7 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
GRTop = DAG.getFrameIndex(FuncInfo->getVarArgsGPRIndex(), PtrVT);
GRTop = DAG.getNode(ISD::ADD, DL, PtrVT, GRTop,
- DAG.getConstant(GPRSize, DL, PtrVT));
+ DAG.getSignedConstant(GPRSize, DL, PtrVT));
GRTop = DAG.getZExtOrTrunc(GRTop, DL, PtrMemVT);
MemOps.push_back(DAG.getStore(Chain, DL, GRTop, GRTopAddr,
@@ -11162,7 +11163,7 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
VRTop = DAG.getFrameIndex(FuncInfo->getVarArgsFPRIndex(), PtrVT);
VRTop = DAG.getNode(ISD::ADD, DL, PtrVT, VRTop,
- DAG.getConstant(FPRSize, DL, PtrVT));
+ DAG.getSignedConstant(FPRSize, DL, PtrVT));
VRTop = DAG.getZExtOrTrunc(VRTop, DL, PtrMemVT);
MemOps.push_back(DAG.getStore(Chain, DL, VRTop, VRTopAddr,
@@ -11175,7 +11176,7 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
SDValue GROffsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getConstant(Offset, DL, PtrVT));
MemOps.push_back(
- DAG.getStore(Chain, DL, DAG.getConstant(-GPRSize, DL, MVT::i32),
+ DAG.getStore(Chain, DL, DAG.getSignedConstant(-GPRSize, DL, MVT::i32),
GROffsAddr, MachinePointerInfo(SV, Offset), Align(4)));
// int __vr_offs at offset 28 (16 on ILP32)
@@ -11183,7 +11184,7 @@ SDValue AArch64TargetLowering::LowerAAPCS_VASTART(SDValue Op,
SDValue VROffsAddr = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
DAG.getConstant(Offset, DL, PtrVT));
MemOps.push_back(
- DAG.getStore(Chain, DL, DAG.getConstant(-FPRSize, DL, MVT::i32),
+ DAG.getStore(Chain, DL, DAG.getSignedConstant(-FPRSize, DL, MVT::i32),
VROffsAddr, MachinePointerInfo(SV, Offset), Align(4)));
return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
@@ -15620,7 +15621,7 @@ SDValue AArch64TargetLowering::LowerATOMIC_LOAD_AND(SDValue Op,
assert(VT != MVT::i128 && "Handled elsewhere, code replicated.");
SDValue RHS = Op.getOperand(2);
AtomicSDNode *AN = cast<AtomicSDNode>(Op.getNode());
- RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getConstant(-1ULL, dl, VT), RHS);
+ RHS = DAG.getNode(ISD::XOR, dl, VT, DAG.getAllOnesConstant(dl, VT), RHS);
return DAG.getAtomic(ISD::ATOMIC_LOAD_CLR, dl, AN->getMemoryVT(),
Op.getOperand(0), Op.getOperand(1), RHS,
AN->getMemOperand());
@@ -21506,7 +21507,7 @@ static SDValue tryConvertSVEWideCompare(SDNode *N, ISD::CondCode CC,
if (auto *CN = dyn_cast<ConstantSDNode>(Comparator.getOperand(0))) {
int64_t ImmVal = CN->getSExtValue();
if (ImmVal >= -16 && ImmVal <= 15)
- Imm = DAG.getConstant(ImmVal, DL, MVT::i32);
+ Imm = DAG.getSignedConstant(ImmVal, DL, MVT::i32);
else
return SDValue();
}
@@ -24400,7 +24401,7 @@ static SDValue performSETCCCombine(SDNode *N,
// this pattern will get better opt in emitComparison
uint64_t TstImm = -1ULL << LHS->getConstantOperandVal(1);
SDValue TST = DAG.getNode(ISD::AND, DL, TstVT, LHS->getOperand(0),
- DAG.getConstant(TstImm, DL, TstVT));
+ DAG.getSignedConstant(TstImm, DL, TstVT));
return DAG.getNode(ISD::SETCC, DL, VT, TST, RHS, N->getOperand(2));
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index a9324af5beb78..a5fae8029deab 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -2214,7 +2214,7 @@ def s64imm_32bit : ImmLeaf<i64, [{
}]>;
def trunc_imm : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
+ return CurDAG->getTargetConstant((uint32_t)N->getZExtValue(), SDLoc(N), MVT::i32);
}]>;
def gi_trunc_imm : GICustomOperandRenderer<"renderTruncImm">,
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