[llvm] [AMDGPU][True16] added Pre-RA hint to improve copy elimination (PR #103366)

[Brox Chen via llvm-commits]

broxigarchen wrote:

> > The allocation order of 16 bit registers is vgpr0lo16, vgpr0hi16, vgpr1lo16, vgpr1hi16, vgpr2lo16.... We prefer (essentially require) that allocation order, because it uses the minimum number of registers. But when you have 16 bit data passing between 16 and 32 bit instructions you get lots of COPY.
> 
> Is this not already the order in the classes? You can explicitly override the allocation order on the register class definition

I think it's already implemented in this way. This patch is to address the additional COPY issue when 16bit data being passed between 16 and 32bit instructions

https://github.com/llvm/llvm-project/pull/103366