[llvm] [AMDGPU][True16] added Pre-RA hint to improve copy elimination (PR #103366)

[Matt Arsenault via llvm-commits]

arsenm wrote:

> The allocation order of 16 bit registers is vgpr0lo16, vgpr0hi16, vgpr1lo16, vgpr1hi16, vgpr2lo16.... We prefer (essentially require) that allocation order, because it uses the minimum number of registers. But when you have 16 bit data passing between 16 and 32 bit instructions you get lots of COPY.

Is this not already the order in the classes? You can explicitly override the allocation order on the register class definition 

https://github.com/llvm/llvm-project/pull/103366