[llvm] [RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (PR #104574)

[Luke Lau via llvm-commits]

lukel97 wrote:

> For reverse operations in vectorizer, I think we can generate strided load/store with negative stride for some cases. 

I was thinking that as well, I haven't fully looked into why the loop vectorizer doesn't just do that.

> SiFive p470 and p670 are quadratic in the worst case, but will skip reading input registers when they aren't used.

I would be happy to gate this behind a "HasOptimizedVrgather" feature, enabled for the spacemit-x60 by default.

https://github.com/llvm/llvm-project/pull/104574