[llvm] [ScheduleDAG] Dirty height/depth in addPred/removePred even for latency zero (PR #102915)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon commented:

Your explanation makes sense to me, but I'm not very familiar with this code @MatzeB any thoughts?

https://github.com/llvm/llvm-project/pull/102915