[llvm] [Attributor][FIX] Ensure we do not use stale references (PR #104495)
Johannes Doerfert via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 15 13:11:55 PDT 2024
https://github.com/jdoerfert created https://github.com/llvm/llvm-project/pull/104495
When copying map entries, we might run into resizing and invalidate the RHS of the assignment. We dealt with this before and now use the proper helper to avoid the problem in another place.
Fixes: https://github.com/llvm/llvm-project/issues/104397
>From 9e16d17d4e916b7a94eabeafe7d299739f0b60b3 Mon Sep 17 00:00:00 2001
From: Johannes Doerfert <johannes at jdoerfert.de>
Date: Thu, 15 Aug 2024 13:06:28 -0700
Subject: [PATCH] [Attributor][FIX] Ensure we do not use stale references
When copying map entries, we might run into resizing and invalidate the
RHS of the assignment. We dealt with this before and now use the proper
helper to avoid the problem in another place.
Fixes: https://github.com/llvm/llvm-project/issues/104397
---
.../Transforms/IPO/AttributorAttributes.cpp | 7 +-
.../aapointer_info_map_invalidation.ll | 588 ++++++++++++++++++
2 files changed, 593 insertions(+), 2 deletions(-)
create mode 100644 llvm/test/Transforms/Attributor/reduced/aapointer_info_map_invalidation.ll
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 41a7fc0870cf0a..9f033028347f0d 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -1628,6 +1628,8 @@ ChangeStatus AAPointerInfoFloating::updateImpl(Attributor &A) {
<< "\n");
assert(OffsetInfoMap.count(CurPtr) &&
"The current pointer offset should have been seeded!");
+ assert(!OffsetInfoMap[CurPtr].isUnassigned() &&
+ "Current pointer should be assigned");
if (ConstantExpr *CE = dyn_cast<ConstantExpr>(Usr)) {
if (CE->isCast())
@@ -1906,6 +1908,7 @@ ChangeStatus AAPointerInfoFloating::updateImpl(Attributor &A) {
};
auto EquivalentUseCB = [&](const Use &OldU, const Use &NewU) {
assert(OffsetInfoMap.count(OldU) && "Old use should be known already!");
+ assert(!OffsetInfoMap[OldU].isUnassigned() && "Old use should be assinged");
if (OffsetInfoMap.count(NewU)) {
LLVM_DEBUG({
if (!(OffsetInfoMap[NewU] == OffsetInfoMap[OldU])) {
@@ -1916,8 +1919,8 @@ ChangeStatus AAPointerInfoFloating::updateImpl(Attributor &A) {
});
return OffsetInfoMap[NewU] == OffsetInfoMap[OldU];
}
- OffsetInfoMap[NewU] = OffsetInfoMap[OldU];
- return true;
+ bool Unused;
+ return HandlePassthroughUser(NewU.get(), OldU.get(), Unused);
};
if (!A.checkForAllUses(UsePred, *this, AssociatedValue,
/* CheckBBLivenessOnly */ true, DepClassTy::OPTIONAL,
diff --git a/llvm/test/Transforms/Attributor/reduced/aapointer_info_map_invalidation.ll b/llvm/test/Transforms/Attributor/reduced/aapointer_info_map_invalidation.ll
new file mode 100644
index 00000000000000..a7622143c2e736
--- /dev/null
+++ b/llvm/test/Transforms/Attributor/reduced/aapointer_info_map_invalidation.ll
@@ -0,0 +1,588 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes --check-attributes
+; RUN: opt -passes=attributor -S < %s | FileCheck %s --check-prefixes=CHECK
+
+define amdgpu_kernel void @__omp_offloading_fd00_2c00523__ZN11qmcplusplus7ompBLAS9gemv_implIfEEiRiciiT_PKS3_iS5_iS3_PS3_i_l383() {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
+; CHECK-LABEL: define {{[^@]+}}@__omp_offloading_fd00_2c00523__ZN11qmcplusplus7ompBLAS9gemv_implIfEEiRiciiT_PKS3_iS5_iS3_PS3_i_l383
+; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca [0 x [0 x float]], i32 0, align 8, addrspace(5)
+; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(5) [[TMP1]] to ptr
+; CHECK-NEXT: store ptr [[TMP2]], ptr addrspace(5) [[TMP1]], align 8
+; CHECK-NEXT: [[TMP3:%.*]] = call fastcc i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr nocapture nofree noundef readonly align 8 dereferenceable_or_null(8) [[TMP2]], i1 noundef false)
+; CHECK-NEXT: ret void
+;
+ %1 = alloca [0 x [0 x float]], i32 0, align 8, addrspace(5)
+ %2 = addrspacecast ptr addrspace(5) %1 to ptr
+ store ptr %2, ptr addrspace(5) %1, align 8
+ %3 = call fastcc i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr %2, i1 false)
+ ret void
+}
+
+define fastcc i32 @__kmpc_nvptx_parallel_reduce_nowait_v2(ptr %0, i1 %1) {
+; CHECK: Function Attrs: mustprogress nofree norecurse nosync nounwind willreturn
+; CHECK-LABEL: define {{[^@]+}}@__kmpc_nvptx_parallel_reduce_nowait_v2
+; CHECK-SAME: (ptr nocapture nofree nonnull readonly align 8 dereferenceable(8) [[TMP0:%.*]], i1 noundef [[TMP1:%.*]]) #[[ATTR0]] {
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP3:%.*]], label [[TMP79:%.*]]
+; CHECK: 3:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP4:%.*]], label [[TMP6:%.*]]
+; CHECK: 4:
+; CHECK-NEXT: [[TMP5:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP5]], align 8
+; CHECK-NEXT: br label [[TMP77:%.*]]
+; CHECK: 6:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP7:%.*]], label [[TMP9:%.*]]
+; CHECK: 7:
+; CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 9:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP10:%.*]], label [[TMP12:%.*]]
+; CHECK: 10:
+; CHECK-NEXT: [[TMP11:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 12:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP13:%.*]], label [[TMP15:%.*]]
+; CHECK: 13:
+; CHECK-NEXT: [[TMP14:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 15:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP16:%.*]], label [[TMP18:%.*]]
+; CHECK: 16:
+; CHECK-NEXT: [[TMP17:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP17]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 18:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP19:%.*]], label [[TMP21:%.*]]
+; CHECK: 19:
+; CHECK-NEXT: [[TMP20:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP20]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 21:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP22:%.*]], label [[TMP24:%.*]]
+; CHECK: 22:
+; CHECK-NEXT: [[TMP23:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP23]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 24:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP25:%.*]], label [[TMP27:%.*]]
+; CHECK: 25:
+; CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP26]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 27:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP28:%.*]], label [[TMP30:%.*]]
+; CHECK: 28:
+; CHECK-NEXT: [[TMP29:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP29]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 30:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP31:%.*]], label [[TMP33:%.*]]
+; CHECK: 31:
+; CHECK-NEXT: [[TMP32:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP32]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 33:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP34:%.*]], label [[TMP36:%.*]]
+; CHECK: 34:
+; CHECK-NEXT: [[TMP35:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP35]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 36:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP37:%.*]], label [[TMP39:%.*]]
+; CHECK: 37:
+; CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP38]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 39:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP40:%.*]], label [[TMP42:%.*]]
+; CHECK: 40:
+; CHECK-NEXT: [[TMP41:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP41]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 42:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP43:%.*]], label [[TMP45:%.*]]
+; CHECK: 43:
+; CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP44]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 45:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP46:%.*]], label [[TMP48:%.*]]
+; CHECK: 46:
+; CHECK-NEXT: [[TMP47:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP47]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 48:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP49:%.*]], label [[TMP51:%.*]]
+; CHECK: 49:
+; CHECK-NEXT: [[TMP50:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP50]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 51:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP52:%.*]], label [[TMP54:%.*]]
+; CHECK: 52:
+; CHECK-NEXT: [[TMP53:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP53]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 54:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP55:%.*]], label [[TMP57:%.*]]
+; CHECK: 55:
+; CHECK-NEXT: [[TMP56:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP56]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 57:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP58:%.*]], label [[TMP60:%.*]]
+; CHECK: 58:
+; CHECK-NEXT: [[TMP59:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP59]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 60:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP61:%.*]], label [[TMP63:%.*]]
+; CHECK: 61:
+; CHECK-NEXT: [[TMP62:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP62]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 63:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP64:%.*]], label [[TMP66:%.*]]
+; CHECK: 64:
+; CHECK-NEXT: [[TMP65:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP65]], align 8
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 66:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP67:%.*]], label [[TMP69:%.*]]
+; CHECK: 67:
+; CHECK-NEXT: [[TMP68:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP68]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 69:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP70:%.*]], label [[TMP72:%.*]]
+; CHECK: 70:
+; CHECK-NEXT: [[TMP71:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP71]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 72:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP73:%.*]], label [[TMP75:%.*]]
+; CHECK: 73:
+; CHECK-NEXT: [[TMP74:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP74]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 75:
+; CHECK-NEXT: [[TMP76:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP76]], align 4
+; CHECK-NEXT: br label [[TMP77]]
+; CHECK: 77:
+; CHECK-NEXT: [[TMP78:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP78]], align 4
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP80:%.*]], label [[TMP82:%.*]]
+; CHECK: 79:
+; CHECK-NEXT: ret i32 0
+; CHECK: 80:
+; CHECK-NEXT: [[TMP81:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP81]], align 8
+; CHECK-NEXT: ret i32 0
+; CHECK: 82:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP83:%.*]], label [[TMP85:%.*]]
+; CHECK: 83:
+; CHECK-NEXT: [[TMP84:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP84]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 85:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP86:%.*]], label [[TMP88:%.*]]
+; CHECK: 86:
+; CHECK-NEXT: [[TMP87:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP87]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 88:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP89:%.*]], label [[TMP91:%.*]]
+; CHECK: 89:
+; CHECK-NEXT: [[TMP90:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP90]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 91:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP92:%.*]], label [[TMP94:%.*]]
+; CHECK: 92:
+; CHECK-NEXT: [[TMP93:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP93]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 94:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP95:%.*]], label [[TMP97:%.*]]
+; CHECK: 95:
+; CHECK-NEXT: [[TMP96:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP96]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 97:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP98:%.*]], label [[TMP100:%.*]]
+; CHECK: 98:
+; CHECK-NEXT: [[TMP99:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP99]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 100:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP101:%.*]], label [[TMP103:%.*]]
+; CHECK: 101:
+; CHECK-NEXT: [[TMP102:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP102]], align 8
+; CHECK-NEXT: ret i32 0
+; CHECK: 103:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP104:%.*]], label [[TMP106:%.*]]
+; CHECK: 104:
+; CHECK-NEXT: [[TMP105:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP105]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 106:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP107:%.*]], label [[TMP109:%.*]]
+; CHECK: 107:
+; CHECK-NEXT: [[TMP108:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP108]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 109:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP110:%.*]], label [[TMP112:%.*]]
+; CHECK: 110:
+; CHECK-NEXT: [[TMP111:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP111]], align 4
+; CHECK-NEXT: ret i32 0
+; CHECK: 112:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP113:%.*]], label [[TMP115:%.*]]
+; CHECK: 113:
+; CHECK-NEXT: [[TMP114:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP114]], align 8
+; CHECK-NEXT: ret i32 0
+; CHECK: 115:
+; CHECK-NEXT: br i1 [[TMP1]], label [[TMP116:%.*]], label [[TMP118:%.*]]
+; CHECK: 116:
+; CHECK-NEXT: [[TMP117:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i64 0, ptr [[TMP117]], align 8
+; CHECK-NEXT: ret i32 0
+; CHECK: 118:
+; CHECK-NEXT: [[TMP119:%.*]] = load ptr, ptr [[TMP0]], align 8
+; CHECK-NEXT: store i32 0, ptr [[TMP119]], align 4
+; CHECK-NEXT: ret i32 0
+;
+ br i1 %1, label %3, label %88
+
+3: ; preds = %2
+ %4 = load ptr, ptr %0, align 8
+ br i1 %1, label %5, label %7
+
+5: ; preds = %3
+ %6 = load ptr, ptr %0, align 8
+ store i64 0, ptr %6, align 8
+ br label %79
+
+7: ; preds = %3
+ br i1 %1, label %8, label %11
+
+8: ; preds = %7
+ %9 = load i32, ptr %4, align 4
+ %10 = load ptr, ptr %0, align 8
+ store i32 0, ptr %10, align 4
+ br label %79
+
+11: ; preds = %7
+ br i1 %1, label %12, label %14
+
+12: ; preds = %11
+ %13 = load ptr, ptr %0, align 8
+ store i32 0, ptr %13, align 4
+ br label %79
+
+14: ; preds = %11
+ br i1 %1, label %15, label %17
+
+15: ; preds = %14
+ %16 = load ptr, ptr %0, align 8
+ store i32 0, ptr %16, align 4
+ br label %79
+
+17: ; preds = %14
+ br i1 %1, label %18, label %20
+
+18: ; preds = %17
+ %19 = load ptr, ptr %0, align 8
+ store i32 0, ptr %19, align 4
+ br label %79
+
+20: ; preds = %17
+ br i1 %1, label %21, label %23
+
+21: ; preds = %20
+ %22 = load ptr, ptr %0, align 8
+ store i32 0, ptr %22, align 4
+ br label %79
+
+23: ; preds = %20
+ br i1 %1, label %24, label %26
+
+24: ; preds = %23
+ %25 = load ptr, ptr %0, align 8
+ store i32 0, ptr %25, align 4
+ br label %79
+
+26: ; preds = %23
+ br i1 %1, label %27, label %29
+
+27: ; preds = %26
+ %28 = load ptr, ptr %0, align 8
+ store i32 0, ptr %28, align 8
+ br label %79
+
+29: ; preds = %26
+ br i1 %1, label %30, label %32
+
+30: ; preds = %29
+ %31 = load ptr, ptr %0, align 8
+ store i32 0, ptr %31, align 4
+ br label %79
+
+32: ; preds = %29
+ br i1 %1, label %33, label %35
+
+33: ; preds = %32
+ %34 = load ptr, ptr %0, align 8
+ store i32 0, ptr %34, align 4
+ br label %79
+
+35: ; preds = %32
+ br i1 %1, label %36, label %38
+
+36: ; preds = %35
+ %37 = load ptr, ptr %0, align 8
+ store i32 0, ptr %37, align 4
+ br label %79
+
+38: ; preds = %35
+ br i1 %1, label %39, label %41
+
+39: ; preds = %38
+ %40 = load ptr, ptr %0, align 8
+ store i64 0, ptr %40, align 8
+ br label %79
+
+41: ; preds = %38
+ br i1 %1, label %42, label %44
+
+42: ; preds = %41
+ %43 = load ptr, ptr %0, align 8
+ store i64 0, ptr %43, align 8
+ br label %79
+
+44: ; preds = %41
+ br i1 %1, label %45, label %47
+
+45: ; preds = %44
+ %46 = load ptr, ptr %0, align 8
+ store i32 0, ptr %46, align 4
+ br label %79
+
+47: ; preds = %44
+ br i1 %1, label %48, label %50
+
+48: ; preds = %47
+ %49 = load ptr, ptr %0, align 8
+ store i32 0, ptr %49, align 4
+ br label %79
+
+50: ; preds = %47
+ br i1 %1, label %51, label %53
+
+51: ; preds = %50
+ %52 = load ptr, ptr %0, align 8
+ store i64 0, ptr %52, align 8
+ br label %79
+
+53: ; preds = %50
+ br i1 %1, label %54, label %56
+
+54: ; preds = %53
+ %55 = load ptr, ptr %0, align 8
+ store i64 0, ptr %55, align 8
+ br label %79
+
+56: ; preds = %53
+ br i1 %1, label %57, label %59
+
+57: ; preds = %56
+ %58 = load ptr, ptr %0, align 8
+ store i32 0, ptr %58, align 4
+ br label %79
+
+59: ; preds = %56
+ br i1 %1, label %60, label %62
+
+60: ; preds = %59
+ %61 = load ptr, ptr %0, align 8
+ store i32 0, ptr %61, align 4
+ br label %79
+
+62: ; preds = %59
+ br i1 %1, label %63, label %65
+
+63: ; preds = %62
+ %64 = load ptr, ptr %0, align 8
+ store i64 0, ptr %64, align 8
+ br label %79
+
+65: ; preds = %62
+ br i1 %1, label %66, label %68
+
+66: ; preds = %65
+ %67 = load ptr, ptr %0, align 8
+ store i64 0, ptr %67, align 8
+ br label %79
+
+68: ; preds = %65
+ br i1 %1, label %69, label %71
+
+69: ; preds = %68
+ %70 = load ptr, ptr %0, align 8
+ store i32 0, ptr %70, align 4
+ br label %79
+
+71: ; preds = %68
+ br i1 %1, label %72, label %74
+
+72: ; preds = %71
+ %73 = load ptr, ptr %0, align 8
+ store i32 0, ptr %73, align 4
+ br label %79
+
+74: ; preds = %71
+ br i1 %1, label %75, label %77
+
+75: ; preds = %74
+ %76 = load ptr, ptr %0, align 8
+ store i32 0, ptr %76, align 4
+ br label %79
+
+77: ; preds = %74
+ %78 = load ptr, ptr %0, align 8
+ store i32 0, ptr %78, align 4
+ br label %79
+
+79: ; preds = %77, %75, %72, %69, %66, %63, %60, %57, %54, %51, %48, %45, %42, %39, %36, %33, %30, %27, %24, %21, %18, %15, %12, %8, %5
+ %80 = load ptr, ptr %0, align 8
+ %81 = load i32, ptr %80, align 4
+ %82 = load ptr, ptr %0, align 8
+ store i32 0, ptr %82, align 4
+ %83 = load ptr, ptr %0, align 8
+ %84 = getelementptr i8, ptr %83, i64 4
+ %85 = load ptr, ptr %0, align 8
+ %86 = getelementptr i8, ptr %85, i64 4
+ %87 = load ptr, ptr %0, align 8
+ br i1 %1, label %91, label %93
+
+88: ; preds = %2
+ %89 = load ptr, ptr %0, align 8
+ %90 = load i64, ptr %89, align 8
+ ret i32 0
+
+91: ; preds = %79
+ %92 = load ptr, ptr %0, align 8
+ store i64 0, ptr %92, align 8
+ ret i32 0
+
+93: ; preds = %79
+ br i1 %1, label %94, label %96
+
+94: ; preds = %93
+ %95 = load ptr, ptr %0, align 8
+ store i32 0, ptr %95, align 4
+ ret i32 0
+
+96: ; preds = %93
+ br i1 %1, label %97, label %99
+
+97: ; preds = %96
+ %98 = load ptr, ptr %0, align 8
+ store i32 0, ptr %98, align 4
+ ret i32 0
+
+99: ; preds = %96
+ br i1 %1, label %100, label %102
+
+100: ; preds = %99
+ %101 = load ptr, ptr %0, align 8
+ store i32 0, ptr %101, align 4
+ ret i32 0
+
+102: ; preds = %99
+ br i1 %1, label %103, label %105
+
+103: ; preds = %102
+ %104 = load ptr, ptr %0, align 8
+ store i32 0, ptr %104, align 4
+ ret i32 0
+
+105: ; preds = %102
+ br i1 %1, label %106, label %108
+
+106: ; preds = %105
+ %107 = load ptr, ptr %0, align 8
+ store i32 0, ptr %107, align 4
+ ret i32 0
+
+108: ; preds = %105
+ br i1 %1, label %109, label %111
+
+109: ; preds = %108
+ %110 = load ptr, ptr %0, align 8
+ store i32 0, ptr %110, align 4
+ ret i32 0
+
+111: ; preds = %108
+ br i1 %1, label %112, label %114
+
+112: ; preds = %111
+ %113 = load ptr, ptr %0, align 8
+ store i32 0, ptr %113, align 8
+ ret i32 0
+
+114: ; preds = %111
+ br i1 %1, label %115, label %117
+
+115: ; preds = %114
+ %116 = load ptr, ptr %0, align 8
+ store i32 0, ptr %116, align 4
+ ret i32 0
+
+117: ; preds = %114
+ br i1 %1, label %118, label %121
+
+118: ; preds = %117
+ %119 = load i32, ptr %87, align 4
+ %120 = load ptr, ptr %0, align 8
+ store i32 0, ptr %120, align 4
+ ret i32 0
+
+121: ; preds = %117
+ br i1 %1, label %122, label %124
+
+122: ; preds = %121
+ %123 = load ptr, ptr %0, align 8
+ store i32 0, ptr %123, align 4
+ ret i32 0
+
+124: ; preds = %121
+ br i1 %1, label %125, label %127
+
+125: ; preds = %124
+ %126 = load ptr, ptr %0, align 8
+ store i64 0, ptr %126, align 8
+ ret i32 0
+
+127: ; preds = %124
+ br i1 %1, label %128, label %130
+
+128: ; preds = %127
+ %129 = load ptr, ptr %0, align 8
+ store i64 0, ptr %129, align 8
+ ret i32 0
+
+130: ; preds = %127
+ %131 = load ptr, ptr %0, align 8
+ store i32 0, ptr %131, align 4
+ ret i32 0
+}
+
+; uselistorder directives
+uselistorder i32 0, { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 0 }
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