[llvm] [RISCV][GISel] Remove s32 support on RV64 for DIV, and REM. (PR #102519)

[Michael Maitland via llvm-commits]

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@@ -348,7 +348,9 @@ define i32 @sdiv_i32(i32 %a, i32 %b) {
 ;
 ; RV64IM-LABEL: sdiv_i32:
 ; RV64IM:       # %bb.0: # %entry
-; RV64IM-NEXT:    divw a0, a0, a1
+; RV64IM-NEXT:    sext.w a0, a0
+; RV64IM-NEXT:    sext.w a1, a1
+; RV64IM-NEXT:    div a0, a0, a1
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michaelmaitland wrote:

What if we look at it during custom legalization?

https://github.com/llvm/llvm-project/pull/102519