[llvm] [TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (PR #101751)

[Simon Pilgrim via llvm-commits]

https://github.com/RKSimon approved this pull request.

LGTM - as it looks like the AArch32/Thumb2 diffs are acceptable by the ARM team

https://github.com/llvm/llvm-project/pull/101751