[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[David Green via llvm-commits]

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@@ -0,0 +1,109 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-unknwon-linux-gnu -mattr=+sve2 -O3 %s -o - | FileCheck %s
+
+target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+target triple = "aarch64-none-unknown-elf"
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davemgreen wrote:

This doesn't match the run line, and datalayout is often unnecessary in llc tests.

https://github.com/llvm/llvm-project/pull/101010