[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[David Green via llvm-commits]

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@@ -21237,6 +21279,83 @@ static SDValue performIntrinsicCombine(SDNode *N,
   switch (IID) {
   default:
     break;
+  case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc DL(N);
+
+    bool IsValidDotProduct = true;
+
+    auto NarrowOp = N->getOperand(1);
+    auto MulOp = N->getOperand(2);
+    if (MulOp->getOpcode() != ISD::MUL)
+      IsValidDotProduct = false;
+
+    auto ExtA = MulOp->getOperand(0);
+    auto ExtB = MulOp->getOperand(1);
+    bool IsSExt = ExtA->getOpcode() == ISD::SIGN_EXTEND;
+    bool IsZExt = ExtA->getOpcode() == ISD::ZERO_EXTEND;
+    if (ExtA->getOpcode() != ExtB->getOpcode() || (!IsSExt && !IsZExt))
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davemgreen wrote:

Check the types too?

https://github.com/llvm/llvm-project/pull/101010