[llvm] [AArch64] Lower partial add reduction to udot or svdot (PR #101010)

[Sam Tebbs via llvm-commits]

================
@@ -21237,6 +21279,32 @@ static SDValue performIntrinsicCombine(SDNode *N,
   switch (IID) {
   default:
     break;
+  case Intrinsic::experimental_vector_partial_reduce_add: {
+    SDLoc DL(N);
+
+    auto NarrowOp = N->getOperand(1);
----------------
SamTebbs33 wrote:

Thanks Dave, I've now added a fallback that creates a chain of ADDs if the nodes aren't as expected.

https://github.com/llvm/llvm-project/pull/101010