[llvm] [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (PR #102034)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/102034

>From fdb760e8fa895514ecd2c53fc58203a6d7e61a5b Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 5 Aug 2024 11:29:31 -0700
Subject: [PATCH 1/2] [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x,
 c2-c3), c3) isel in some cases.

If x is a shl by 32 and c1 is an simm12, we would prefer to use a
SRAIW+ANDI. This prevents selecting the slli to a separate slli
instruction.
---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp     | 6 +++++-
 llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll | 5 ++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 3dcfeecec1e75..b140d72e36fed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1460,7 +1460,11 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
 
       SDValue X = N0.getOperand(0);
 
-      if (isMask_64(C1)) {
+      // Prefer SRAIW + ANDI when possible.
+      bool Skip = C2 > 32 && IsC1ANDI && X.getOpcode() == ISD::SHL &&
+                  isa<ConstantSDNode>(X.getOperand(1)) &&
+                  X.getConstantOperandVal(1) == 32;
+      if (isMask_64(C1) && !Skip) {
         unsigned Leading = XLen - llvm::bit_width(C1);
         if (C2 > Leading) {
           SDNode *SRAI = CurDAG->getMachineNode(
diff --git a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
index 4749cc656693c..0d96fbfa81279 100644
--- a/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
+++ b/llvm/test/CodeGen/RISCV/selectcc-to-shiftand.ll
@@ -276,9 +276,8 @@ define i64 @sraiw_andi(i32 signext %0, i32 signext %1) nounwind {
 ; RV64-LABEL: sraiw_andi:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    add a0, a0, a1
-; RV64-NEXT:    slli a0, a0, 32
-; RV64-NEXT:    srai a0, a0, 2
-; RV64-NEXT:    srli a0, a0, 61
+; RV64-NEXT:    sraiw a0, a0, 31
+; RV64-NEXT:    andi a0, a0, 7
 ; RV64-NEXT:    ret
 entry:
   %3 = add i32 %0, %1

>From c6ddc9516b187be3fb5681ca7e93e48b21d793eb Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 5 Aug 2024 16:05:42 -0700
Subject: [PATCH 2/2] fixup! Rebase.

---
 llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 82a233ebad5ab..604234b243153 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -1462,7 +1462,8 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       SDValue X = N0.getOperand(0);
 
       // Prefer SRAIW + ANDI when possible.
-      bool Skip = C2 > 32 && IsC1ANDI && X.getOpcode() == ISD::SHL &&
+      bool Skip = C2 > 32 && isInt<12>(N1C->getSExtValue()) &&
+                  X.getOpcode() == ISD::SHL &&
                   isa<ConstantSDNode>(X.getOperand(1)) &&
                   X.getConstantOperandVal(1) == 32;
       if (isMask_64(C1) && !Skip) {