[llvm] [RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (PR #102034)

[Yingwei Zheng via llvm-commits]

dtcxzyw wrote:

Can you rebase this patch over https://github.com/llvm/llvm-project/commit/cfd13cbac12b73069c79c89bb37294f77938bb3f?

```
/home/dtcxzyw/WorkSpace/Projects/compilers/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp: In member function ‘virtual void llvm::RISCVDAGToDAGISel::Select(llvm::SDNode*)’:
/home/dtcxzyw/WorkSpace/Projects/compilers/llvm-project/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:1465: error: ‘IsC1ANDI’ was not declared in this scope
 1465 |       bool Skip = C2 > 32 && IsC1ANDI && X.getOpcode() == ISD::SHL &&
      | 
ninja: build stopped: subcommand failed.
```

https://github.com/llvm/llvm-project/pull/102034