[llvm] [RISCV] Support llvm.masked.expandload intrinsic (PR #101954)

[Pengcheng Wang via llvm-commits]

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@@ -10760,16 +10762,38 @@ SDValue RISCVTargetLowering::lowerMaskedLoad(SDValue Op,
   if (!VL)
     VL = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget).second;
 
-  unsigned IntID =
-      IsUnmasked ? Intrinsic::riscv_vle : Intrinsic::riscv_vle_mask;
+  SDValue Index;
+  if (!IsUnmasked && IsExpandingLoad) {
+    MVT IndexVT = ContainerVT;
+    if (ContainerVT.isFloatingPoint())
+      IndexVT = IndexVT.changeVectorElementTypeToInteger();
+
+    if (Subtarget.isRV32() && IndexVT.getVectorElementType().bitsGT(XLenVT))
+      IndexVT = IndexVT.changeVectorElementType(XLenVT);
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wangpc-pp wrote:

Yes, we can construct such tests like:
```
define <1024 x i8> @test_expandload_v1024i8(ptr %base, <1024 x i1> %mask, <1024 x i8> %passthru) "target-features"="+zvl1024b" {
  %res = call <1024 x i8> @llvm.masked.expandload.v1024i8(ptr align 1 %base, <1024 x i1> %mask, <1024 x i8> %passthru)
  ret <1024 x i8> %res
}
```
But I don't know how to make it legal because we can't just change `IndexVT` to be with element type `MVT::i16` as the changed `IndexVT` will be an illegal type. For example, from `nxv64i8` to `nxv64i16`(illegal).
I tried to split it to small ones but failed. Do you have any thought on fixing this or can we just ignore it?

https://github.com/llvm/llvm-project/pull/101954